APA-Zitierstil (7. Ausg.)

Tripathi, S. L., Saxena, S., Sinha, S. K., & Patel, G. S. (2022). Digital VLSI design and simulation with Verilog. John Wiley & Sons, Inc.

Chicago-Zitierstil (17. Ausg.)

Tripathi, Suman Lata, Sobhit Saxena, Sanjeet Kumar Sinha, und Govind Singh Patel. Digital VLSI Design and Simulation with Verilog. Hoboken, NJ: John Wiley & Sons, Inc, 2022.

MLA-Zitierstil (9. Ausg.)

Tripathi, Suman Lata, et al. Digital VLSI Design and Simulation with Verilog. John Wiley & Sons, Inc, 2022.