Digital VLSI design and simulation with Verilog:
"The integrated circuits are now growing its importance in every electronic system that needs an efficient VLSI architecture designs with low power consumption, compress chip area, speed, and operating frequency. The challenge for VLSI system designers is to optimize the hardware-software integ...
Gespeichert in:
| Beteiligte Personen: | , , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | Englisch |
| Veröffentlicht: |
Hoboken, NJ
John Wiley & Sons, Inc.
2022
|
| Schlagwörter: | |
| Links: | https://learning.oreilly.com/library/view/-/9781119778042/?ar |
| Zusammenfassung: | "The integrated circuits are now growing its importance in every electronic system that needs an efficient VLSI architecture designs with low power consumption, compress chip area, speed, and operating frequency. The challenge for VLSI system designers is to optimize the hardware-software integration for lowering the total cost of acquisition of products. So, there is a demand for better technological solutions for advanced VLSI architectures that can be done through hardware description language (HDL). Verilog HDL is one of the programming languages that can give better solutions to this new era of the VLSI industry. The prefabrication design and analysis of such advanced VLSI architecture can be easily implemented with Verilog HDL with the available software tools like Xilinx and Cadence. The presented book mainly deals with fundamental concepts of digital design along with their design verification with Verilog HDL. The book will be a common source of knowledge for the beginners as well as research seeking students working in the area of VLSI design covering fundamentals of digital design from switch level to FPGA based implementation using hardware description language (HDL). The book is summarized in 10 chapters. Chapter 1 and 2 describes the fundamental concepts behind digital circuit design including combinational and sequential circuit design. Chapter 3 to chapter 8 is focused on sequential and combinational circuit design using Verilog HDL at a different level of abstractions in Verilog coding. Chapter 9 includes implementation of any logic function using a programmable logic device like PLD, CPLD or FPGA, etc. Chapter 10 covers a few real-time examples of digital circuit design using Verilog. Chapter 11 focuses on System Verilog, distinct features, computing Verilog and System Verilog with design example."-- |
| Beschreibung: | Includes bibliographical references and index. - Description based on online resource; title from digital title page (viewed on April 14, 2022) |
| Umfang: | 1 Online-Ressource |
| ISBN: | 9781119778097 1119778093 9781119778066 1119778069 1119778085 9781119778080 9781119778042 |
Internformat
MARC
| LEADER | 00000cam a22000002 4500 | ||
|---|---|---|---|
| 001 | ZDB-30-ORH-07659551X | ||
| 003 | DE-627-1 | ||
| 005 | 20240228121349.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 220209s2022 xx |||||o 00| ||eng c | ||
| 020 | |a 9781119778097 |c electronic book |9 978-1-119-77809-7 | ||
| 020 | |a 1119778093 |c electronic book |9 1-119-77809-3 | ||
| 020 | |a 9781119778066 |c electronic book |9 978-1-119-77806-6 | ||
| 020 | |a 1119778069 |c electronic book |9 1-119-77806-9 | ||
| 020 | |a 1119778085 |c electronic book |9 1-119-77808-5 | ||
| 020 | |a 9781119778080 |c electronic bk. |9 978-1-119-77808-0 | ||
| 020 | |a 9781119778042 |9 978-1-119-77804-2 | ||
| 035 | |a (DE-627-1)07659551X | ||
| 035 | |a (DE-599)KEP07659551X | ||
| 035 | |a (ORHE)9781119778042 | ||
| 035 | |a (DE-627-1)07659551X | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rda | ||
| 041 | |a eng | ||
| 082 | 0 | |a 621.39/5028553 |2 23 | |
| 100 | 1 | |a Tripathi, Suman Lata |e VerfasserIn |4 aut | |
| 245 | 1 | 0 | |a Digital VLSI design and simulation with Verilog |c Suman Lata Tripathi, Sobhit Saxena, Sanjeet Kumar Sinha, Govind Singh Patel |
| 264 | 1 | |a Hoboken, NJ |b John Wiley & Sons, Inc. |c 2022 | |
| 264 | 4 | |c ©2022 | |
| 300 | |a 1 Online-Ressource | ||
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a Computermedien |b c |2 rdamedia | ||
| 338 | |a Online-Ressource |b cr |2 rdacarrier | ||
| 500 | |a Includes bibliographical references and index. - Description based on online resource; title from digital title page (viewed on April 14, 2022) | ||
| 520 | |a "The integrated circuits are now growing its importance in every electronic system that needs an efficient VLSI architecture designs with low power consumption, compress chip area, speed, and operating frequency. The challenge for VLSI system designers is to optimize the hardware-software integration for lowering the total cost of acquisition of products. So, there is a demand for better technological solutions for advanced VLSI architectures that can be done through hardware description language (HDL). Verilog HDL is one of the programming languages that can give better solutions to this new era of the VLSI industry. The prefabrication design and analysis of such advanced VLSI architecture can be easily implemented with Verilog HDL with the available software tools like Xilinx and Cadence. The presented book mainly deals with fundamental concepts of digital design along with their design verification with Verilog HDL. The book will be a common source of knowledge for the beginners as well as research seeking students working in the area of VLSI design covering fundamentals of digital design from switch level to FPGA based implementation using hardware description language (HDL). The book is summarized in 10 chapters. Chapter 1 and 2 describes the fundamental concepts behind digital circuit design including combinational and sequential circuit design. Chapter 3 to chapter 8 is focused on sequential and combinational circuit design using Verilog HDL at a different level of abstractions in Verilog coding. Chapter 9 includes implementation of any logic function using a programmable logic device like PLD, CPLD or FPGA, etc. Chapter 10 covers a few real-time examples of digital circuit design using Verilog. Chapter 11 focuses on System Verilog, distinct features, computing Verilog and System Verilog with design example."-- | ||
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design and construction | |
| 650 | 0 | |a Verilog (Computer hardware description language) | |
| 650 | 4 | |a Verilog (Langage de description de matériel informatique) | |
| 650 | 4 | |a Integrated circuits ; Very large scale integration ; Design and construction | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 700 | 1 | |a Saxena, Sobhit |e VerfasserIn |4 aut | |
| 700 | 1 | |a Sinha, Sanjeet Kumar |e VerfasserIn |4 aut | |
| 700 | 1 | |a Patel, Govind Singh |e VerfasserIn |4 aut | |
| 776 | 1 | |z 9781119778042 | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781119778042 |
| 966 | 4 | 0 | |l DE-91 |p ZDB-30-ORH |q TUM_PDA_ORH |u https://learning.oreilly.com/library/view/-/9781119778042/?ar |m X:ORHE |x Aggregator |z lizenzpflichtig |3 Volltext |
| 912 | |a ZDB-30-ORH | ||
| 912 | |a ZDB-30-ORH | ||
| 951 | |a BO | ||
| 912 | |a ZDB-30-ORH | ||
| 049 | |a DE-91 | ||
Datensatz im Suchindex
| DE-BY-TUM_katkey | ZDB-30-ORH-07659551X |
|---|---|
| _version_ | 1821494825194618880 |
| adam_text | |
| any_adam_object | |
| author | Tripathi, Suman Lata Saxena, Sobhit Sinha, Sanjeet Kumar Patel, Govind Singh |
| author_facet | Tripathi, Suman Lata Saxena, Sobhit Sinha, Sanjeet Kumar Patel, Govind Singh |
| author_role | aut aut aut aut |
| author_sort | Tripathi, Suman Lata |
| author_variant | s l t sl slt s s ss s k s sk sks g s p gs gsp |
| building | Verbundindex |
| bvnumber | localTUM |
| collection | ZDB-30-ORH |
| ctrlnum | (DE-627-1)07659551X (DE-599)KEP07659551X (ORHE)9781119778042 |
| dewey-full | 621.39/5028553 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5028553 |
| dewey-search | 621.39/5028553 |
| dewey-sort | 3621.39 75028553 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>04143cam a22005412 4500</leader><controlfield tag="001">ZDB-30-ORH-07659551X</controlfield><controlfield tag="003">DE-627-1</controlfield><controlfield tag="005">20240228121349.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">220209s2022 xx |||||o 00| ||eng c</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781119778097</subfield><subfield code="c">electronic book</subfield><subfield code="9">978-1-119-77809-7</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1119778093</subfield><subfield code="c">electronic book</subfield><subfield code="9">1-119-77809-3</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781119778066</subfield><subfield code="c">electronic book</subfield><subfield code="9">978-1-119-77806-6</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1119778069</subfield><subfield code="c">electronic book</subfield><subfield code="9">1-119-77806-9</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1119778085</subfield><subfield code="c">electronic book</subfield><subfield code="9">1-119-77808-5</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781119778080</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">978-1-119-77808-0</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781119778042</subfield><subfield code="9">978-1-119-77804-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627-1)07659551X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)KEP07659551X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ORHE)9781119778042</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627-1)07659551X</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5028553</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Tripathi, Suman Lata</subfield><subfield code="e">VerfasserIn</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Digital VLSI design and simulation with Verilog</subfield><subfield code="c">Suman Lata Tripathi, Sobhit Saxena, Sanjeet Kumar Sinha, Govind Singh Patel</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Hoboken, NJ</subfield><subfield code="b">John Wiley & Sons, Inc.</subfield><subfield code="c">2022</subfield></datafield><datafield tag="264" ind1=" " ind2="4"><subfield code="c">©2022</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references and index. - Description based on online resource; title from digital title page (viewed on April 14, 2022)</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">"The integrated circuits are now growing its importance in every electronic system that needs an efficient VLSI architecture designs with low power consumption, compress chip area, speed, and operating frequency. The challenge for VLSI system designers is to optimize the hardware-software integration for lowering the total cost of acquisition of products. So, there is a demand for better technological solutions for advanced VLSI architectures that can be done through hardware description language (HDL). Verilog HDL is one of the programming languages that can give better solutions to this new era of the VLSI industry. The prefabrication design and analysis of such advanced VLSI architecture can be easily implemented with Verilog HDL with the available software tools like Xilinx and Cadence. The presented book mainly deals with fundamental concepts of digital design along with their design verification with Verilog HDL. The book will be a common source of knowledge for the beginners as well as research seeking students working in the area of VLSI design covering fundamentals of digital design from switch level to FPGA based implementation using hardware description language (HDL). The book is summarized in 10 chapters. Chapter 1 and 2 describes the fundamental concepts behind digital circuit design including combinational and sequential circuit design. Chapter 3 to chapter 8 is focused on sequential and combinational circuit design using Verilog HDL at a different level of abstractions in Verilog coding. Chapter 9 includes implementation of any logic function using a programmable logic device like PLD, CPLD or FPGA, etc. Chapter 10 covers a few real-time examples of digital circuit design using Verilog. Chapter 11 focuses on System Verilog, distinct features, computing Verilog and System Verilog with design example."--</subfield></datafield><datafield tag="650" ind1=" " ind2="0"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="0"><subfield code="a">Verilog (Computer hardware description language)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Verilog (Langage de description de matériel informatique)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits ; Very large scale integration ; Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Verilog (Computer hardware description language)</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Saxena, Sobhit</subfield><subfield code="e">VerfasserIn</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Sinha, Sanjeet Kumar</subfield><subfield code="e">VerfasserIn</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Patel, Govind Singh</subfield><subfield code="e">VerfasserIn</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="1" ind2=" "><subfield code="z">9781119778042</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781119778042</subfield></datafield><datafield tag="966" ind1="4" ind2="0"><subfield code="l">DE-91</subfield><subfield code="p">ZDB-30-ORH</subfield><subfield code="q">TUM_PDA_ORH</subfield><subfield code="u">https://learning.oreilly.com/library/view/-/9781119778042/?ar</subfield><subfield code="m">X:ORHE</subfield><subfield code="x">Aggregator</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-30-ORH</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-30-ORH</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">BO</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-30-ORH</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield></datafield></record></collection> |
| id | ZDB-30-ORH-07659551X |
| illustrated | Not Illustrated |
| indexdate | 2025-01-17T11:20:32Z |
| institution | BVB |
| isbn | 9781119778097 1119778093 9781119778066 1119778069 1119778085 9781119778080 9781119778042 |
| language | English |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM |
| owner_facet | DE-91 DE-BY-TUM |
| physical | 1 Online-Ressource |
| psigel | ZDB-30-ORH TUM_PDA_ORH ZDB-30-ORH |
| publishDate | 2022 |
| publishDateSearch | 2022 |
| publishDateSort | 2022 |
| publisher | John Wiley & Sons, Inc. |
| record_format | marc |
| spelling | Tripathi, Suman Lata VerfasserIn aut Digital VLSI design and simulation with Verilog Suman Lata Tripathi, Sobhit Saxena, Sanjeet Kumar Sinha, Govind Singh Patel Hoboken, NJ John Wiley & Sons, Inc. 2022 ©2022 1 Online-Ressource Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Includes bibliographical references and index. - Description based on online resource; title from digital title page (viewed on April 14, 2022) "The integrated circuits are now growing its importance in every electronic system that needs an efficient VLSI architecture designs with low power consumption, compress chip area, speed, and operating frequency. The challenge for VLSI system designers is to optimize the hardware-software integration for lowering the total cost of acquisition of products. So, there is a demand for better technological solutions for advanced VLSI architectures that can be done through hardware description language (HDL). Verilog HDL is one of the programming languages that can give better solutions to this new era of the VLSI industry. The prefabrication design and analysis of such advanced VLSI architecture can be easily implemented with Verilog HDL with the available software tools like Xilinx and Cadence. The presented book mainly deals with fundamental concepts of digital design along with their design verification with Verilog HDL. The book will be a common source of knowledge for the beginners as well as research seeking students working in the area of VLSI design covering fundamentals of digital design from switch level to FPGA based implementation using hardware description language (HDL). The book is summarized in 10 chapters. Chapter 1 and 2 describes the fundamental concepts behind digital circuit design including combinational and sequential circuit design. Chapter 3 to chapter 8 is focused on sequential and combinational circuit design using Verilog HDL at a different level of abstractions in Verilog coding. Chapter 9 includes implementation of any logic function using a programmable logic device like PLD, CPLD or FPGA, etc. Chapter 10 covers a few real-time examples of digital circuit design using Verilog. Chapter 11 focuses on System Verilog, distinct features, computing Verilog and System Verilog with design example."-- Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Verilog (Langage de description de matériel informatique) Integrated circuits ; Very large scale integration ; Design and construction Saxena, Sobhit VerfasserIn aut Sinha, Sanjeet Kumar VerfasserIn aut Patel, Govind Singh VerfasserIn aut 9781119778042 Erscheint auch als Druck-Ausgabe 9781119778042 |
| spellingShingle | Tripathi, Suman Lata Saxena, Sobhit Sinha, Sanjeet Kumar Patel, Govind Singh Digital VLSI design and simulation with Verilog Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Verilog (Langage de description de matériel informatique) Integrated circuits ; Very large scale integration ; Design and construction |
| title | Digital VLSI design and simulation with Verilog |
| title_auth | Digital VLSI design and simulation with Verilog |
| title_exact_search | Digital VLSI design and simulation with Verilog |
| title_full | Digital VLSI design and simulation with Verilog Suman Lata Tripathi, Sobhit Saxena, Sanjeet Kumar Sinha, Govind Singh Patel |
| title_fullStr | Digital VLSI design and simulation with Verilog Suman Lata Tripathi, Sobhit Saxena, Sanjeet Kumar Sinha, Govind Singh Patel |
| title_full_unstemmed | Digital VLSI design and simulation with Verilog Suman Lata Tripathi, Sobhit Saxena, Sanjeet Kumar Sinha, Govind Singh Patel |
| title_short | Digital VLSI design and simulation with Verilog |
| title_sort | digital vlsi design and simulation with verilog |
| topic | Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Verilog (Langage de description de matériel informatique) Integrated circuits ; Very large scale integration ; Design and construction |
| topic_facet | Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Verilog (Langage de description de matériel informatique) Integrated circuits ; Very large scale integration ; Design and construction |
| work_keys_str_mv | AT tripathisumanlata digitalvlsidesignandsimulationwithverilog AT saxenasobhit digitalvlsidesignandsimulationwithverilog AT sinhasanjeetkumar digitalvlsidesignandsimulationwithverilog AT patelgovindsingh digitalvlsidesignandsimulationwithverilog |