Formal verification: an essential toolkit for modern VLSI design
Gespeichert in:
| Beteiligte Personen: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | Englisch |
| Veröffentlicht: |
Waltham, MA
Elsevier Science
[2015]
|
| Schlagwörter: | |
| Links: | https://learning.oreilly.com/library/view/-/9780128008157/?ar |
| Beschreibung: | Includes bibliographical references and index. - Online resource; title from title page (Safari, viewed August 18, 2015) |
| Umfang: | 1 Online-Ressource (1 volume) illustrations |
| ISBN: | 9780128008157 0128008156 0128007273 9780128007273 |
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| spelling | Seligman, Erik VerfasserIn aut Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar Essential toolkit for modern VLSI design Waltham, MA Elsevier Science [2015] ©2015 1 Online-Ressource (1 volume) illustrations Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Includes bibliographical references and index. - Online resource; title from title page (Safari, viewed August 18, 2015) Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Verilog (Langage de description de matériel informatique) Electronic circuits ; Testing Integrated circuits ; Very large scale integration ; Design and construction Schubert, E. Thomas 1959- VerfasserIn aut Kumar, M. V. Achutha Kiran VerfasserIn aut |
| spellingShingle | Seligman, Erik Schubert, E. Thomas 1959- Kumar, M. V. Achutha Kiran Formal verification an essential toolkit for modern VLSI design Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Verilog (Langage de description de matériel informatique) Electronic circuits ; Testing Integrated circuits ; Very large scale integration ; Design and construction |
| title | Formal verification an essential toolkit for modern VLSI design |
| title_alt | Essential toolkit for modern VLSI design |
| title_auth | Formal verification an essential toolkit for modern VLSI design |
| title_exact_search | Formal verification an essential toolkit for modern VLSI design |
| title_full | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_fullStr | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_full_unstemmed | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_short | Formal verification |
| title_sort | formal verification an essential toolkit for modern vlsi design |
| title_sub | an essential toolkit for modern VLSI design |
| topic | Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Verilog (Langage de description de matériel informatique) Electronic circuits ; Testing Integrated circuits ; Very large scale integration ; Design and construction |
| topic_facet | Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Verilog (Langage de description de matériel informatique) Electronic circuits ; Testing Integrated circuits ; Very large scale integration ; Design and construction |
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