Verfügbarkeit: Invasive computing | Technische Universität München

Invasive computing:

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Bibliographische Detailangaben
Weitere beteiligte Personen:	Teich, Jürgen 1964- (HerausgeberIn)
Format:	Buch
Sprache:	Englisch
Veröffentlicht:	Erlangen FAU University Press 2022
Schlagwörter:	Programmierung Datenverarbeitungssystem Parallelverarbeitung Parallelprogrammierung Dienstgüte Network-on-Chip Chip-Multiprozessor System-on-Chip Ressourcenverwaltung Hardwarebeschleunigung Ablaufplanung Parallel Computing Multicore Computer Architecture Resource-aware Programming Run-time Systems Compilation
Links:	https://open.fau.de/handle/openfau/20033 https://doi.org/10.25593/978-3-96147-571-1 https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-200331 https://d-nb.info/1266414916/34 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033829258&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
Umfang:	ix, 431 Seiten Illustrationen, Diagramme 24 cm x 17 cm, 1067 g
ISBN:	9783961475704 3961475709 9783961475711
DOI:	10.25593/978-3-96147-571-1

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Datensatz im Suchindex

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adam_text	CONTENTS I INTRODUCTION TO INVASIVE COMPUTING I JIIRGEN TEICH, JORG HENKEL, ANDREAS HERKERSDORF 1.1 WHAT IS INVASIVE COMPUTING? .......................................................... 2 1.2 LONG-TERM RESEARCH GOALS AND VISION ............................................. 6 1.3 ACHIEVEMENTS IN FIRST AND SECOND FUNDING PHASES (2010-2018) . . 13 1.4 ASSESSMENT OF PROJECT STRUCTURE ........................................................ 41 1.5 RESEARCH FOCUS IN THE THIRD FUNDING PHASE (2018-2022) .............. 43 1.5.1 GOALS AND STRATEGY .................................................................. 43 1.5.2 RESEARCH FOCUS PER PROJECT AREA ........................................... 44 1.5.3 INVASIC VALIDATION AND DEMONSTRATOR ROAD MAP .............. 53 1.5.4 WORKING GROUPS - DEVELOPING CROSS-PROJECT SYNERGIES . . 55 A: FUNDAMENTALS, LANGUAGE AND ALGORITHM RESEARCH 69 2 BASICS OF INVASIVE COMPUTING 69 JIIRGEN TEICH, KHALIL ESPER, JOACHIM FALK, BEHNAZ POURMOHSENI, TOBIAS SCHWARZER, STEFAN WILDERMANN 2.1 RUN-TIME REQUIREMENT ENFORCEMENT (RRE) ..................................... 69 2.2 TAXONOMY OF RUN-TIME REQUIREMENT ENFORCERS .............................. 71 2.3 APPLICATION CHARACTERISATION AND ENFORCEMENT ACTIONS ................. 73 2.4 POWER, LATENCY, AND ENERGY MODEL ..................................................... 74 2.5 ENERGY-MINIMISED TIMING ENFORCEMENT ........................................... 77 2.6 DISTRIBUTED ENFORCEMENT .................................................................. 78 2.7 FEEDBACK-BASED ENFORCEMENT STRATEGIES ........................................... 81 2.7.1 FORMAL DEFINITIONS .............................................................. 82 2.7.2 VERIFICATION GOALS .................................................................. 85 2.7.3 PROPERTY SPECIFICATION IN PRISM ........................................... 87 2.7.4 VERIFICATION RESULTS .............................................................. 88 2.8 CONCLUSIONS AND ACKNOWLEDGEMENT ................................................. 92 3 CHARACTERISATION AND ANALYSIS OF INVASIVE ALGORITHMIC PATTERNS 97 MICHAEL BADER, STEFAN WILDERMANN, MICHAEL GLAFI, ALEXANDER POPPI, BEHNAZ POURMOHSENI, TOBIAS SCHWARZER, JAN SPIECK, MARIO WILLE 3.1 INTRODUCTION ........................................................................................ 97 3.2 ALGORITHMIC PATTERNS ........................................................................... 98 3.2.1 THE SHALLOW WATER EQUATIONS ............................................. 98 3.2.2 SWE-X10 ............................................................................. 100 III 3.3 HYBRID APPLICATION MAPPING .......................................................... 105 3.3.1 COMPLEXITY REDUCTION ........................................................... 107 3.3.2 COMPOSABILITY ........................................................................ 108 3.3.3 MAPPING RECONFIGURATION AND TASK MIGRATION ..................... 109 3.3.4 SCENARIO-AWARE HAM ........................................................... 109 3.4 CONCLUSIONS AND ACKNOWLEDGEMENTS ............................................. 119 4 SCHEDULING INVASIVE MULTICORE PROGRAMS UNDER UNCERTAINTY 123 NICOLE MEGOW, ALEXANDER LINDERMAYR, BERTRAND SIMON 4.1 INTRODUCTION ........................................................................................ 123 4.2 UNCERTAIN EXECUTION TIMES .............................................................. 124 4.2.1 LEARNING-AUGMENTED ALGORITHM DESIGN .......................... 125 4.2.2 PREDICTION MODEL AND ERROR DEFINITION .............................. 127 4.2.3 THE PREFERENTIAL TIME SHARING FRAMEWORK ........................ 129 4.2.4 EXPERIMENTAL EVALUATION .................................................... 131 4.3 UNCERTAIN TASK GRAPHS ........................................................................ 135 4.4 UNCERTAIN PROCESSOR AVAILABILITY OR SPEED ........................................ 139 4.5 SPEED-SCALING FOR RUN-TIME REQUIREMENT ENFORCEMENT AND POWER MANAGEMENT ............................................................................. 142 4.6 CONCLUSION .......................................................................................... 145 B: ARCHITECTURAL RESEARCH 151 5 ADAPTIVE APPLICATION-SPECIFIC INVASIVE MICRO-ARCHITECTURES 151 LARS BAUER, JIIRGEN BECKER, JORG HENKEL, FABIAN LESNIAK, HASSAN NASSAR 5.1 INTRODUCTION ........................................................................................ 151 5.1.1 OVERVIEW OF THE Z-CORE ARCHITECTURE .................................... 152 5.1.2 PROTOTYPE AND INTEGRATION .................................................... 154 5.2 GENERATING AND USING SPECIAL INSTRUCTIONS (SIS) .............................. 154 5.2.1 EXAMPLES FOR SIS AND ACCELERATORS ....................................... 155 5.2.2 AUTOMATIC GENERATION OF SIS DURING RUNTIME .................... 157 5.3 RUN-TIME ADAPTIVE CACHE ARCHITECTURES ........................................... 158 5.3.1 INTRA-TILE CACHE RE-ALLOCATION .......................................... 158 5.3.2 ASSOCIATIVITY AND CACHE SIZE IMPACT .................................... 159 5.4 SECURITY ASPECTS OF THE Z-CORE .......................................................... 161 5.4.1 INFORMATION LEAKAGE PROTECTION .......................................... 161 5.4.2 ISOLATION MODES AND MITIGATION OF VOLTAGE-BASED ATTACKS . 162 5.5 INTRA-TILE MULTICORE EXTENSION FOR THE Z-CORE .................................... 164 5.6 NEAR MEMORY COMPUTING EXTENSIONS ............................................. 165 5.6.1 REGION-BASED NEAR-MEMORY COMPUTING ........................... 166 5.6.2 NEAR-MEMORY COMPUTING (NMC) CONTROLLER ..................... 168 IV 5.6.3 EVALUATION: AES ENCRYPTION PERFORMANCE .......................... 168 5.7 TASK SCHEDULING FOR RUNTIME-RECONFIGURABLE PROCESSORS .............. 169 5.8 WORST CASE EXECUTION TIME ANALYSIS AND OPTIMISATIONS FOR RECON FIGURABLE PROCESSORS ................................................................. 170 5.9 CONCLUSION ............................................................................................ 173 6 INVASIVE TIGHTLY-COUPLED PROCESSOR ARRAYS 177 JIIRGEN TEICH, MARCEL BRAND, FRANK HANNIG, CHRISTIAN HEIDORN, DOMINIK WALTER, MICHAEL WITTERAUF 6.1 INTRODUCTION ........................................................................................ 178 6.2 SAFE(R) LOOPS - FAULT-TOLERANT PARALLEL LOOP PROCESSING .................. 180 6.3 ORTHOGONAL INSTRUCTION PROCESSING ..................................................... 182 6.4 RUN-TIME REQUIREMENT ENFORCEMENT (RRE) ON TCPAS .................. 183 6.5 ANYTIME INSTRUCTION PROCESSORS (AIP) .............................................. 186 6.5.1 ON-LINE ARITHMETIC APPROACH ............................................... 188 6.5.2 BITMASKING APPROACH ............................................................ 189 6.6 REAL-TIME SCHEDULING OF I/O DATA TRANSFERS ..................................... 192 6.6.1 GENERATION OF DATA BLOCKS ..................................................... 193 6.6.2 REAL-TIME I/O SCHEDULING PROBLEM ..................................... 195 6.6.3 LOOP I/O CONTROLLER ............................................................... 197 6.6.4 PRIORITY QUEUE ..................................................................... 197 6.6.5 CONFIGURATION UNIT ............................................................... 199 6.6.6 DMA ENGINE ........................................................................ 199 6.7 CONCLUSIONS AND ACKNOWLEDGEMENT .................................................. 200 7 POWER-EFFICIENT INVASIVE LOOSELY-COUPLED MPSOCS 203 JORG HENKEL, ANDREAS HERKERSDORF, HEBA KHDR, MARTIN RAPP, MARK SAGI, MOHAMMED BAKR SIKAL, THOMAS WILD 7.1 INTRODUCTION ........................................................................................ 203 7.2 THERMALLY SAFE POWER CONSTRAINTS ..................................................... 205 7.3 RULE-BASED POWER/THERMAL MANAGEMENT ........................................ 206 7.3.1 CORE I-LET CONTROLLER ............................................................. 206 7.3.2 THERMAL-CONSTRAINED APPLICATION MAPPING AND VOLTAGE/ FREQUENCY (V/F) SELECTION .................................................... 208 7.4 ML-BASED POWER/THERMAL MANAGEMENT AND MODELLING ..................... 209 7.4.1 APPLICATION MAPPING AND V/F SCALING ................................. 210 7.4.2 POWER AND CACHE-AWARE APPLICATION MIGRATION .............. 213 7.4.3 APPLICATION-AWARE BOOSTING ................................................ 216 7.4.4 RUN-TIME POWER ESTIMATION AND FORECASTING .................... 219 7.5 CONCLUSION ........................................................................................... 225 V 8 GENERATION OF DISTRIBUTED MONITORS AND RUN-TIME VERIFICATION OF INVASIVE APPLICATIONS 229 DANIEL MIILLER-GRITSCHNEDER, ULF SCHLICHTMANN, ALEXANDRA LISTL, MARCEL METTLER, LI ZHANG 8.1 INTRODUCTION ........................................................................................ 229 8.2 RUN-TIME VERIFICATION OF INVASIVE MANY-CORE SYSTEMS ..................... 230 8.2.1 SUPPORTED RUN-TIME REQUIREMENTS .................................... 231 8.2.2 ARCHITECTURAL DESIGN .......................................................... 233 8.2.3 BENEFITS AND LIMITATIONS OF THE RUN-TIME VERIFICATION (RV) SYSTEM .................................................................................... 238 8.3 THERMAL EMULATION OF ASICS ON FPGA PROTOTYPES .......................... 239 8.3.1 ASIC POWER EMULATION ....................................................... 240 8.3.2 ASIC TEMPERATURE EMULATION .............................................. 241 8.3.3 ASIC DYNAMIC VOLTAGE FREQUENCY SCALING EMULATION . . . 243 8.4 GENERATION OF INVASIVE APPLICATIONS ................................................. 245 8.5 FPGA-BASED EVALUATION OF STRATEGIES FOR THERMAL AND RESOURCE MAN AGEMENT .................................................................................... 248 8.6 CONCLUSION .......................................................................................... 251 9 INVASIVE NOCS AND MEMORY HIERARCHIES FOR RUN-TIME ADAPTIVE MPSOCS 255 JIIRGEN BECKER, ANDREAS HERKERSDORF, NIDHI ANANTHARAJAIAH, OLIVER LENKE, AKSHAY SRIVATSA, THOMAS WILD 9.1 INTRODUCTION ....................................................................................... 255 9.2 INOC AS BASIC INVASIVE INTERCONNECT ................................................ 257 9.3 ADAPTIVE MULTI-LAYERED NOC AND DYNAMIC MULTICAST SUPPORT . . . 258 9.3.1 MULTI-LAYERED TOPOLOGIES .................................................... 258 9.3.2 ADAPTIVE CONGESTION-AWARE ROUTING ALGORITHM ................. 260 9.3.3 DYNAMIC BLOCK-BASED MULTICAST ROUTING ........................... 261 9.4 ADAPTIVE NOC BASED ON ANT COLONY OPTIMISATION ......................... 264 9.4.1 DISTRIBUTED ROUTING BASED ON ANT COLONY OPTIMISATION . 265 9.5 REGION-BASED CACHE COHERENCE ....................................................... 268 9.5.1 CONCEPT ................................................................................. 268 9.5.2 FEATURES ................................................................................. 268 9.5.3 DESIGN AND FUNCTIONALITY .................................................... 270 9.5.4 EVALUATION .............................................................................. 271 9.6 NEAR-MEMORY COMPUTING ................................................................ 273 9.6.1 CONCEPT OF NEAR-MEMORY GRAPH COPY .............................. 275 9.6.2 IMPLEMENTATION ..................................................................... 276 9.6.3 EVALUATION .............................................................................. 277 9.7 CONCLUSION AND ACKNOWLEDGEMENT ................................................ 279 VI C: COMPILER, SIMULATION AND RUN-TIME SUPPORT 285 10 INVASIVE RUN-TIME SUPPORT SYSTEM (IRTSS) 285 LARS BAUER, JORG HENKEL, TIMO HONIG, WOLFGANG SCHRODER-PREIKSCHAT, CHRISTIAN EICHLER, JEFERSON GONZALEZ, BENEDICT HERZOG, TOBIAS LANGER, SEBASTIAN MAIER, JONAS RABENSTEIN, PHILLIP RAFFECK, FLORIAN SCHMAUS 10.1 INTRODUCTION ........................................................................................ 285 10.2 OCTOPOS ............................................................................................... 286 10.2.1 MEMORY AND ADDRESS SPACES ............................................. 287 10.2.2 PROCESSES AND THREADS .......................................................... 292 10.2.3 TIME AND ENERGY ................................................................. 295 10.2.4 EVALUATION OF THE CONCEPTS ................................................. 296 10.3 AGENT SYSTEM ..................................................................................... 298 10.3.1 EXPRESSING RESOURCE REQUIREMENTS AND SCALABILITY BY CON STRAINT SYSTEMS .................................................................... 298 10.3.2 DECENTRALISED AGENT SYSTEM (AS) INFRASTRUCTURE ................ 299 10.3.3 RESOURCE MANAGEMENT FOR COMPLEX CONSTRAINTS ............. 300 10.3.4 RESOURCE MANAGEMENT FOR MALLEABLE APPLICATIONS .... 301 10.3.5 ADAPTIVE ON-THE-FLY APPLICATION PERFORMANCE MODEL . . . 303 10.3.6 ENFORCING SECURITY THROUGH RESOURCE MANAGEMENT .... 304 10.4 ACKNOWLEDGEMENT ............................................................................. 305 11 COMPILATION AND CODE GENERATION FOR INVASIVE PROGRAMS 309 GREGOR SNELTING, JIIRGEN TEICH, ANDREAS FRIED, FRANK HANNIG, MICHAEL WITTERAUF 11.1 INTRODUCTION ........................................................................................ 309 11.2 SYMBOLIC LOOP COMPILATION FOR TCPAS .............................................. 311 11.2.1 POLYHEDRAL MODEL .................................................................. 313 11.2.2 SYMBOLIC MAPPING ................................................................. 314 11.2.3 INSTANTIATION ........................................................................ 317 11.2.4 RUN-TIME REQUIREMENT ENFORCEMENT ON LOOPS ................. 319 11.3 COMPILATION FOR GENERAL-PURPOSE CPUS ............................................ 322 11.3.1 INVASIVE X10 FRONT END ........................................................ 322 11.3.2 PGAS PROGRAMMING ON IRTSS .............................................. 324 11.4 COMPILER OPTIMISATIONS .................................................................... 325 11.4.1 A NEW ALGORITHM FOR SSA CONSTRUCTION .............................. 325 11.4.2 COMPILER SYNTHESIS .............................................................. 325 11.4.3 REGISTER PERMUTATIONS ........................................................... 327 U.4.4 OPTIMISING INTER-TILE DATA TRANSFER .................................... 328 11.4.5 NEAR-MEMORY COMPUTING .................................................... 330 11.5 ACKNOWLEDGEMENT .............................................................................. 331 VII 12 SECURITY IN INVASIVE COMPUTING SYSTEMS 335 FELIX FREILING, WOLFGANG SCHRODER-PREIKSCHAT, GREGOR SNELTING, INGRID VERBAUWHEDE, FRANZISKA SCHIRRMACHER, FURKAN TURAN, SIMON BISCHOF 12.1 INTRODUCTION ....................................................................................... 335 12.2 ATTACKER MODEL ................................................................................ 336 12.3 SECURITY REQUIREMENTS AND ISOLATION CONCEPTS ............................ 337 12.3.1 CONFIDENTIALITY REQUIREMENTS ............................................... 338 12.3.2 INTEGRITY REQUIREMENTS ........................................................ 339 12.3.3 ISOLATION CONCEPTS .................................................................. 339 12.4 PREVIOUS WORK ................................................................................... 340 12.4.1 APPLICATION AND SYSTEMS SOFTWARE LAYER ........................... 340 12.4.2 HARDWARE LAYER ..................................................................... 342 12.5 INFORMATION FLOW CONTROL VIA CONTROL FLOW ATTESTATION ............... 345 12.6 LANGUAGE-BASED INFORMATION FLOW CONTROL ................................... 347 12.6.1 TIMING-SENSITIVE INFORMATION FLOW CONTROL ........................ 347 12.6.2 INFORMATION FLOW CONTROL FOR PARALLEL PROGRAMS .................. 348 12.6.3 QUANTITATIVE INFORMATION FLOW ............................................ 349 12.7 RUN-TIME MONITORING FOR SIDE-CHANNEL DETECTION ...................... 350 12.8 VIRTUAL SHARED MEMORY ENCRYPTION, INTEGRITY AND ACCESS ............ 351 12.9 HARDWARE-BASED MUTUAL ATTESTATION ................................................ 352 12.10 SUMMARY AND ACKNOWLEDGEMENTS .................................................... 353 D : APPLICATIONS 359 13 INVASIVE SOFTWARE-HARDWARE ARCHITECTURES FOR ROBOTICS 359 TAMIM ASFOUR, WALTER STECHELE, NAEL FASFOUS, FELIX HUNDHAUSEN, FABIAN PAUS 13.1 INTRODUCTION ...................................................................................... 359 13.2 FEATURE DETECTION ............................................................................. 360 13.3 OBJECT CLASSIFICATION AND SEGMENTATION ......................................... 362 13.4 LOW-LATENCY RUN-TIME ADAPTABLE BINARY NEURAL NETWORK CLASSIFIER 365 13.5 MOTION PLANNING ................................................................................ 370 13.6 EXTRACTING SUPPORT RELATIONS ......................................................... 374 13.7 ACTION EFFECT PREDICTION ................................................................... 377 13.8 NETWORK AND ROBOT CO-SIMULATION ................................................ 378 13.9 CONCLUSION AND ACKNOWLEDGEMENT ................................................ 379 14 INVASIVE COMPUTING AND HPC 383 MICHAEL BADER, HANS-JOACHIM BUNGARTZ, MICHAEL GERNDT, JOPHIN JOHN, SANTIAGO NARVAEZ RIVAS, ISAIAS A. COMPRES URENA 14.1 CHALLENGES AND OPPORTUNITIES .......................................................... 383 VIII 14.2 INVASIVE COMPUTING WITHIN AN HPC NODE ....................................... 386 14.2.1 IOPENMP CONCEPTS .............................................................. 386 14.2.2 IOPENMP IMPLEMENTATION ................................................. 387 14.2.3 APPLICATIONS ........................................................................... 388 14.3 INVASIVE COMPUTING FOR LARGE SCALE HPC SYSTEMS .......................... 389 14.3.1 IMPI CONCEPTS ........................................................................ 389 14.3.2 IMPI IMPLEMENTATION ........................................................... 390 14.3.3 APPLICATIONS ........................................................................... 392 14.3.4 ELASTIC-PHASE ORIENTED PROGRAMMING MODEL ......................... 394 14.4 DATA CENTRE LEVEL INVASIVE SERVICES ................................................. 396 14.4.1 ENABLING INTERACTIVE WORKLOADS ........................................... 396 14.4.2 POWER CORRIDOR MANAGEMENT .............................................. 398 14.4.3 INVASIVE CHECKPOINTING ........................................................ 401 14.5 INTEGRATING IMPI WITH THE X86 NATIVE OCTOPOS PLATFORM ............. 405 14.5.1 APPROACH .............................................................................. 405 14.5.2 IMPLEMENTATION ..................................................................... 406 14.5.3 APPLICATIONS ........................................................................... 406 14.6 SUMMARY AND OUTLOOK ....................................................................... 408 5 VALIDATION AND DEMONSTRATOR 411 JIIRGEN BECKER, FRANK HANNIG, THOMAS WILD, MARCEL BRAND, OLIVER LENKE, FABIAN LESNIAK 15.1 INTRODUCTION ........................................................................................ 411 15.2 FPGA PROTOTYPING PLATFORM .............................................................. 413 15.2.1 INTER-FPGA PIN MULTIPLEXING .............................................. 413 15.2.2 MEMORY AND INTERFACING ........................................................ 414 15.2.3 CONFIGURATION AND DEBUGGING .............................................. 415 15.3 INVASIVE ARCHITECTURE PROTOTYPE ....................................................... 415 15.3.1 INVASIVE NETWORK-ON-CHIP . ................................................... 417 15.3.2 PROCESSOR TILES ........................................................................ 417 15.3.3 Z-CORE TILES ........................................................................... 420 15.3.4 TCPA TILES .............................................................................. 420 15.3.5 SHARED MEMORY TILE .............................................................. 421 15.3.6 I/O TILES ................................................................................. 421 15.3.7 ADDRESS MAPPING ................................................................. 421 15.3.8 NON-INTRUSIVE MONITORING SYSTEM ........................................ 422 15.4 INTEGRATION PROCEDURE AND DEBUGGING .............................................. 423 15.5 INVASIVE COMPUTING DEMONSTRATORS ................................................. 424 15.5.1 ENFORCEMENT DEMONSTRATOR ................................................. 425 15.5.2 PROSTHETIC HAND DEMONSTRATOR ........................................... 429 15.6 CONCLUSION AND ACKNOWLEDGEMENT ................................................. 430 IX
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id	DE-604.BV048451107
illustrated	Illustrated
indexdate	2024-12-20T19:45:20Z
institution	BVB
institution_GND	(DE-588)1068111240
isbn	9783961475704 3961475709 9783961475711
language	English
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-033829258
oclc_num	1343010421
open_access_boolean	1
owner	DE-29 DE-12 DE-29T DE-860 DE-91 DE-BY-TUM
owner_facet	DE-29 DE-12 DE-29T DE-860 DE-91 DE-BY-TUM
physical	ix, 431 Seiten Illustrationen, Diagramme 24 cm x 17 cm, 1067 g
psigel	ebook
publishDate	2022
publishDateSearch	2022
publishDateSort	2022
publisher	FAU University Press
record_format	marc
spellingShingle	Invasive computing Programmierung (DE-588)4076370-5 gnd Datenverarbeitungssystem (DE-588)4125229-9 gnd Parallelverarbeitung (DE-588)4075860-6 gnd
subject_GND	(DE-588)4076370-5 (DE-588)4125229-9 (DE-588)4075860-6
title	Invasive computing
title_alt	Invasives Rechnen
title_auth	Invasive computing
title_exact_search	Invasive computing
title_full	Invasive computing Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.)
title_fullStr	Invasive computing Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.)
title_full_unstemmed	Invasive computing Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Eds.)
title_short	Invasive computing
title_sort	invasive computing
topic	Programmierung (DE-588)4076370-5 gnd Datenverarbeitungssystem (DE-588)4125229-9 gnd Parallelverarbeitung (DE-588)4075860-6 gnd
topic_facet	Programmierung Datenverarbeitungssystem Parallelverarbeitung
url	https://open.fau.de/handle/openfau/20033 https://doi.org/10.25593/978-3-96147-571-1 https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-200331 https://d-nb.info/1266414916/34 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=033829258&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
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