Verfügbarkeit: Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates:

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Bibliographische Detailangaben
Beteiligte Personen:	Reuben, John (VerfasserIn), Pechmann, Stefan (VerfasserIn)
Format:	Elektronisch E-Book
Sprache:	Englisch
Veröffentlicht:	Erlangen ; Nürnberg Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) 2021
Ausgabe:	Preprint
Links:	https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-161464 https://d-nb.info/1231078030/34 https://open.fau.de/handle/openfau/16146
Umfang:	1 Online-Ressource

Internformat

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spelling	Reuben, John Verfasser aut Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates John Reuben, Stefan Pechmann Preprint Erlangen ; Nürnberg Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) 2021 1 Online-Ressource txt rdacontent c rdamedia cr rdacarrier Archivierung/Langzeitarchivierung gewährleistet DE-101 pdager Pechmann, Stefan Verfasser aut Sonderdruck aus IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10.1109/TVLSI.2021.3068470 https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-161464 Resolving-System kostenfrei Volltext https://d-nb.info/1231078030/34 Langzeitarchivierung Nationalbibliothek kostenfrei Volltext application/pdf https://open.fau.de/handle/openfau/16146 Verlag kostenfrei Volltext PDF 1\p aepkn 0,88113 20210410 DE-101 https://d-nb.info/provenance/plan#aepkn 2\p aepsg 0,94391 20210410 DE-101 https://d-nb.info/provenance/plan#aepsg 3\p npi 20210409 DE-101 https://d-nb.info/provenance/plan#npi
spellingShingle	Reuben, John Pechmann, Stefan Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
title	Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
title_auth	Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
title_exact_search	Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
title_full	Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates John Reuben, Stefan Pechmann
title_fullStr	Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates John Reuben, Stefan Pechmann
title_full_unstemmed	Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates John Reuben, Stefan Pechmann
title_short	Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
title_sort	accelerated addition in resistive ram array using parallel friendly majority gates
url	https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-161464 https://d-nb.info/1231078030/34 https://open.fau.de/handle/openfau/16146
work_keys_str_mv	AT reubenjohn acceleratedadditioninresistiveramarrayusingparallelfriendlymajoritygates AT pechmannstefan acceleratedadditioninresistiveramarrayusingparallelfriendlymajoritygates

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