Data orchestration in deep learning accelerators:
Gespeichert in:
| Beteiligte Personen: | , , , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | Englisch |
| Veröffentlicht: |
[San Rafael]
Morgan & Claypool Publishers
[2020]
|
| Schriftenreihe: | Synthesis lectures on computer architecture
#52 |
| Schlagwörter: | |
| Links: | https://ebookcentral.proquest.com/lib/munchentech/detail.action?docID=6318949 |
| Abstract: | Intro -- Preface -- Acknowledgments -- Introduction to Data Orchestration -- Deep Neural Networks (DNNs) -- DNN Training and Inference -- DNN Architectures and Layer Types -- Popular DNN Models -- DNN Accelerators -- Computations within DNNs -- Challenge: Data Movement -- Opportunity: Data Reuse -- Book Overview -- Dataflow and Data Reuse -- Data Reuse Opportunities -- Data Reuse in 1D Convolution -- Dataflows and Mappings -- Deep Dive into Dataflows and Mappings -- Harnessing Data Reuse via Hardware Support -- Dataflows and Data Reuse in CONV2D -- CONV2D Operation -- Data Dimension Coupling and Data Reuse Opportunities -- Data Reuse in a CONV2D Example -- Convolution as Matrix Multiplication -- Summary -- Buffer Hierarchies -- Motivation -- Classifying Buffering Approaches -- Implicit vs. Explicit Orchestration -- Coupled vs. Decoupled Orchestration -- Synchronization Concerns -- The Buffet Storage Idiom -- Buffet Operational Behavior -- Buffet Synchronization Details -- Example Orchestration with Buffets -- Automatically Deriving Configuration -- Composition of Buffer Idioms -- Buffer Hierarchies -- Sharing Fills via Multicast -- Sharing Physical RAMs Efficiently -- Example of Hierarchical Orchestration -- Other Relevant Buffering Idioms for Accelerators -- Research Needs for Accelerator Buffer Hierarchies -- Summary -- Networks-on-Chip -- Communication Phases -- Traditional Networks-on-Chip -- Topology -- Routing -- Flow Control -- Router Microarchitecture -- Challenges with Traditional NoCs -- Specialized NoCs for DNN Accelerators -- Topology -- Routing -- Flow Control -- Leveraging Reuse via the NoC -- Implications of Temporal Reuse -- Implications of Spatial Reuse -- Tying it Together: From Dataflow to Traffic Flow -- Summary -- Putting it Together: Architecting a DNN Accelerator -- Design Flow -- Target Specs and Constraints |
| Beschreibung: | Description based on publisher supplied metadata and other sources |
| Umfang: | 1 Online-Ressource |
| ISBN: | 9781681738703 |
Internformat
MARC
| LEADER | 00000nam a22000001cb4500 | ||
|---|---|---|---|
| 001 | BV047030890 | ||
| 003 | DE-604 | ||
| 005 | 20201204 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 201126s2020 xx o|||| 00||| eng d | ||
| 020 | |a 9781681738703 |9 978-1-68173-870-3 | ||
| 035 | |a (OCoLC)1225882175 | ||
| 035 | |a (DE-599)KEP055749704 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G | ||
| 084 | |a DAT 708 |2 stub | ||
| 100 | 1 | |a Krishna, Tushar |e Verfasser |0 (DE-588)1206961228 |4 aut | |
| 245 | 1 | 0 | |a Data orchestration in deep learning accelerators |c Tushar Krishna (Georgia Institute of Technology), Hyoukjun Kwon (Georgia Institute of Technology), Angshuman Parashar (NVIDIA), Michael Pellauer (NVIDIA), Ananda Samajdar (Georgia Institute of Technology) |
| 264 | 1 | |a [San Rafael] |b Morgan & Claypool Publishers |c [2020] | |
| 300 | |a 1 Online-Ressource | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 1 | |a Synthesis lectures on computer architecture |v #52 | |
| 500 | |a Description based on publisher supplied metadata and other sources | ||
| 520 | 3 | |a Intro -- Preface -- Acknowledgments -- Introduction to Data Orchestration -- Deep Neural Networks (DNNs) -- DNN Training and Inference -- DNN Architectures and Layer Types -- Popular DNN Models -- DNN Accelerators -- Computations within DNNs -- Challenge: Data Movement -- Opportunity: Data Reuse -- Book Overview -- Dataflow and Data Reuse -- Data Reuse Opportunities -- Data Reuse in 1D Convolution -- Dataflows and Mappings -- Deep Dive into Dataflows and Mappings -- Harnessing Data Reuse via Hardware Support -- Dataflows and Data Reuse in CONV2D -- CONV2D Operation -- Data Dimension Coupling and Data Reuse Opportunities -- Data Reuse in a CONV2D Example -- Convolution as Matrix Multiplication -- Summary -- Buffer Hierarchies -- Motivation -- Classifying Buffering Approaches -- Implicit vs. Explicit Orchestration -- Coupled vs. Decoupled Orchestration -- Synchronization Concerns -- The Buffet Storage Idiom -- Buffet Operational Behavior -- Buffet Synchronization Details -- Example Orchestration with Buffets -- Automatically Deriving Configuration -- Composition of Buffer Idioms -- Buffer Hierarchies -- Sharing Fills via Multicast -- Sharing Physical RAMs Efficiently -- Example of Hierarchical Orchestration -- Other Relevant Buffering Idioms for Accelerators -- Research Needs for Accelerator Buffer Hierarchies -- Summary -- Networks-on-Chip -- Communication Phases -- Traditional Networks-on-Chip -- Topology -- Routing -- Flow Control -- Router Microarchitecture -- Challenges with Traditional NoCs -- Specialized NoCs for DNN Accelerators -- Topology -- Routing -- Flow Control -- Leveraging Reuse via the NoC -- Implications of Temporal Reuse -- Implications of Spatial Reuse -- Tying it Together: From Dataflow to Traffic Flow -- Summary -- Putting it Together: Architecting a DNN Accelerator -- Design Flow -- Target Specs and Constraints | |
| 653 | 0 | |a Electronic books | |
| 700 | 1 | |a Kwon, Hyoukjun |e Verfasser |4 aut | |
| 700 | 1 | |a Parashar, Angshuman |e Verfasser |4 aut | |
| 700 | 1 | |a Pellauer, Michael |e Verfasser |4 aut | |
| 700 | 1 | |a Samajdar, Ananda |e Verfasser |4 aut | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe, Hardcover |z 978-1-68173-871-0 |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe, Paperback |z 978-1-68173-869-7 |
| 830 | 0 | |a Synthesis lectures on computer architecture |v #52 |w (DE-604)BV047042546 |9 52 | |
| 912 | |a ZDB-30-PQE | ||
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-032438162 | |
| 966 | e | |u https://ebookcentral.proquest.com/lib/munchentech/detail.action?docID=6318949 |l DE-91 |p ZDB-30-PQE |q TUM_Einzelkauf |x Aggregator |3 Volltext | |
Datensatz im Suchindex
| DE-BY-TUM_katkey | 2511963 |
|---|---|
| _version_ | 1821936105459548160 |
| any_adam_object | |
| author | Krishna, Tushar Kwon, Hyoukjun Parashar, Angshuman Pellauer, Michael Samajdar, Ananda |
| author_GND | (DE-588)1206961228 |
| author_facet | Krishna, Tushar Kwon, Hyoukjun Parashar, Angshuman Pellauer, Michael Samajdar, Ananda |
| author_role | aut aut aut aut aut |
| author_sort | Krishna, Tushar |
| author_variant | t k tk h k hk a p ap m p mp a s as |
| building | Verbundindex |
| bvnumber | BV047030890 |
| classification_tum | DAT 708 |
| collection | ZDB-30-PQE |
| ctrlnum | (OCoLC)1225882175 (DE-599)KEP055749704 |
| discipline | Informatik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03676nam a22004211cb4500</leader><controlfield tag="001">BV047030890</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20201204 </controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">201126s2020 xx o|||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781681738703</subfield><subfield code="9">978-1-68173-870-3</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1225882175</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)KEP055749704</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 708</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Krishna, Tushar</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)1206961228</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Data orchestration in deep learning accelerators</subfield><subfield code="c">Tushar Krishna (Georgia Institute of Technology), Hyoukjun Kwon (Georgia Institute of Technology), Angshuman Parashar (NVIDIA), Michael Pellauer (NVIDIA), Ananda Samajdar (Georgia Institute of Technology)</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">[San Rafael]</subfield><subfield code="b">Morgan & Claypool Publishers</subfield><subfield code="c">[2020]</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Synthesis lectures on computer architecture</subfield><subfield code="v">#52</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Description based on publisher supplied metadata and other sources</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Intro -- Preface -- Acknowledgments -- Introduction to Data Orchestration -- Deep Neural Networks (DNNs) -- DNN Training and Inference -- DNN Architectures and Layer Types -- Popular DNN Models -- DNN Accelerators -- Computations within DNNs -- Challenge: Data Movement -- Opportunity: Data Reuse -- Book Overview -- Dataflow and Data Reuse -- Data Reuse Opportunities -- Data Reuse in 1D Convolution -- Dataflows and Mappings -- Deep Dive into Dataflows and Mappings -- Harnessing Data Reuse via Hardware Support -- Dataflows and Data Reuse in CONV2D -- CONV2D Operation -- Data Dimension Coupling and Data Reuse Opportunities -- Data Reuse in a CONV2D Example -- Convolution as Matrix Multiplication -- Summary -- Buffer Hierarchies -- Motivation -- Classifying Buffering Approaches -- Implicit vs. Explicit Orchestration -- Coupled vs. Decoupled Orchestration -- Synchronization Concerns -- The Buffet Storage Idiom -- Buffet Operational Behavior -- Buffet Synchronization Details -- Example Orchestration with Buffets -- Automatically Deriving Configuration -- Composition of Buffer Idioms -- Buffer Hierarchies -- Sharing Fills via Multicast -- Sharing Physical RAMs Efficiently -- Example of Hierarchical Orchestration -- Other Relevant Buffering Idioms for Accelerators -- Research Needs for Accelerator Buffer Hierarchies -- Summary -- Networks-on-Chip -- Communication Phases -- Traditional Networks-on-Chip -- Topology -- Routing -- Flow Control -- Router Microarchitecture -- Challenges with Traditional NoCs -- Specialized NoCs for DNN Accelerators -- Topology -- Routing -- Flow Control -- Leveraging Reuse via the NoC -- Implications of Temporal Reuse -- Implications of Spatial Reuse -- Tying it Together: From Dataflow to Traffic Flow -- Summary -- Putting it Together: Architecting a DNN Accelerator -- Design Flow -- Target Specs and Constraints</subfield></datafield><datafield tag="653" ind1=" " ind2="0"><subfield code="a">Electronic books</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kwon, Hyoukjun</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Parashar, Angshuman</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Pellauer, Michael</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Samajdar, Ananda</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe, Hardcover</subfield><subfield code="z">978-1-68173-871-0</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe, Paperback</subfield><subfield code="z">978-1-68173-869-7</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Synthesis lectures on computer architecture</subfield><subfield code="v">#52</subfield><subfield code="w">(DE-604)BV047042546</subfield><subfield code="9">52</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-30-PQE</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-032438162</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://ebookcentral.proquest.com/lib/munchentech/detail.action?docID=6318949</subfield><subfield code="l">DE-91</subfield><subfield code="p">ZDB-30-PQE</subfield><subfield code="q">TUM_Einzelkauf</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV047030890 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T19:07:49Z |
| institution | BVB |
| isbn | 9781681738703 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-032438162 |
| oclc_num | 1225882175 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 1 Online-Ressource |
| psigel | ZDB-30-PQE ZDB-30-PQE TUM_Einzelkauf |
| publishDate | 2020 |
| publishDateSearch | 2020 |
| publishDateSort | 2020 |
| publisher | Morgan & Claypool Publishers |
| record_format | marc |
| series | Synthesis lectures on computer architecture |
| series2 | Synthesis lectures on computer architecture |
| spellingShingle | Krishna, Tushar Kwon, Hyoukjun Parashar, Angshuman Pellauer, Michael Samajdar, Ananda Data orchestration in deep learning accelerators Synthesis lectures on computer architecture |
| title | Data orchestration in deep learning accelerators |
| title_auth | Data orchestration in deep learning accelerators |
| title_exact_search | Data orchestration in deep learning accelerators |
| title_full | Data orchestration in deep learning accelerators Tushar Krishna (Georgia Institute of Technology), Hyoukjun Kwon (Georgia Institute of Technology), Angshuman Parashar (NVIDIA), Michael Pellauer (NVIDIA), Ananda Samajdar (Georgia Institute of Technology) |
| title_fullStr | Data orchestration in deep learning accelerators Tushar Krishna (Georgia Institute of Technology), Hyoukjun Kwon (Georgia Institute of Technology), Angshuman Parashar (NVIDIA), Michael Pellauer (NVIDIA), Ananda Samajdar (Georgia Institute of Technology) |
| title_full_unstemmed | Data orchestration in deep learning accelerators Tushar Krishna (Georgia Institute of Technology), Hyoukjun Kwon (Georgia Institute of Technology), Angshuman Parashar (NVIDIA), Michael Pellauer (NVIDIA), Ananda Samajdar (Georgia Institute of Technology) |
| title_short | Data orchestration in deep learning accelerators |
| title_sort | data orchestration in deep learning accelerators |
| volume_link | (DE-604)BV047042546 |
| work_keys_str_mv | AT krishnatushar dataorchestrationindeeplearningaccelerators AT kwonhyoukjun dataorchestrationindeeplearningaccelerators AT parasharangshuman dataorchestrationindeeplearningaccelerators AT pellauermichael dataorchestrationindeeplearningaccelerators AT samajdarananda dataorchestrationindeeplearningaccelerators |