Durable phase-change memory architectures:
Gespeichert in:
| Weitere beteiligte Personen: | , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Cambridge, MA ; San Diego, CA ; Kidlington, Oxford ; London
Academic Press, an imprint of Elsevier
2020
|
| Ausgabe: | First edition |
| Schriftenreihe: | Advances in computers
volume 118 |
| Schlagwörter: | |
| Links: | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=032199622&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| Umfang: | x, 135 Seiten Illustrationen |
| ISBN: | 9780128187548 |
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| 245 | 1 | 0 | |a Durable phase-change memory architectures |c edited by Marjan Asadinia (University of Arkansas, Fayetteville, AR, United States), Hamid Sarbazi-Azad (Sharif University of Technology and Institute for Research in Fundamental Sciences (IPM), Tehran, Iran) |
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Datensatz im Suchindex
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| adam_text | Contents Preface ¡x 1. Introduction to non-volatile memory technologies 1 Marjan Asadinia and Hamid Sarbazi-Azad 1. Memory hierarchy and non-volatile memory 2 2. Emerging NVM technologies 3 3. PCM technology maturity 4 4. Contributions 5 5. Organization of the book 7 References 8 2. The emerging phase change memory 15 Marjan Asadinia and Hamid Sarbazi-Azad 1. Introduction 15 2. PCM materials/device physics 16 3. Memory cell and array design 18 4. Multi-level-cell phase change memory (MLC PCM) 19 5. Read techniques 21 6. Write techniques 21 7. Reliability 24 References 25 3. Phase-change memory architectures 29 Marjan Asadinia and Hamid Sarbazi-Azad 1. Architecting PCM for main memories 30 2. Tolerating slow writes in PCM 34 3. Wear-leveling for durability 36 4. Secure wear-leveling algorithms 38 5. Error resilience in phase changememories 41 6. Soft error approaches 46 References 47 4. Inter-line level schemes for handling hard errorsin PCMs 49 Marjan Asadinia and Hamid Sarbazi-Azad 1. OD3P: On-demand page paired PCM 50 2. Structure and operation of page paired PCM 51 v
vi____ Contents 3. Fixed pairing algorithm 57 4. Partially-selective pairing algorithm 58 5. Operation of different OD3P mechanisms: Examples 59 6. Line-level OD3P 61 7. Simulation environment and scenarios 62 8. Experimental results 66 9. Hardware overhead and extension for N-bit MLC PCM 75 References 76 Further reading 78 5. Handling hard errors in PCMs by using intra-line level schemes 79 Marjan Asadinia and Hamid Sarbazi-Azad 1. BLESS: A simple and efficient scheme for prolonging PCM lifetime 80 2. Improving the bit flips uniformity 81 3. Tolerating the hard errors 81 4. Write operation in BLESS 85 5. Read operation in BLESS 85 6. Meta-data information 86 7. Evaluation setting 86 8. Methodology 86 9. Evaluated architectures 87 10. Evaluation metrics 88 11. Evaluation results 88 12. Comparison to page-level schemes 92 13. Intra-line level pairing (ILP) 92 14. ILP structure 93 15. Experimental results 95 16. Data block partitioning for recovering stuck-at faults in PCMs 100 17. Tolerating hard errors 102 18. Write operation 104 19. Read operation 104 20. Meta-data information 104 21. Experimental results 105 References 109 6. Addressing issues with MLC phase-change memory 111 Marjan Asadinia and Hamid Sarbazi-Azad 1. Variable resistance spectrum assignment 112 2. The MLC VR-PCM 113
Contents vii 3. Extended VR-PCM Ո7 4. Ultimate design: Reconfigurable VR-PCM 117 5. Hardware implementation issues 6. Simulation results 118 123 7. Process variation and resistance drift References Further reading 130 133 133 About the authors 13S
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| id | DE-604.BV046790684 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T19:01:04Z |
| institution | BVB |
| isbn | 9780128187548 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-032199622 |
| oclc_num | 1164622190 |
| open_access_boolean | |
| owner | DE-355 DE-BY-UBR |
| owner_facet | DE-355 DE-BY-UBR |
| physical | x, 135 Seiten Illustrationen |
| publishDate | 2020 |
| publishDateSearch | 2020 |
| publishDateSort | 2020 |
| publisher | Academic Press, an imprint of Elsevier |
| record_format | marc |
| series | Advances in computers |
| series2 | Advances in computers |
| spellingShingle | Durable phase-change memory architectures Advances in computers Hardware (DE-588)4023422-8 gnd |
| subject_GND | (DE-588)4023422-8 |
| title | Durable phase-change memory architectures |
| title_auth | Durable phase-change memory architectures |
| title_exact_search | Durable phase-change memory architectures |
| title_full | Durable phase-change memory architectures edited by Marjan Asadinia (University of Arkansas, Fayetteville, AR, United States), Hamid Sarbazi-Azad (Sharif University of Technology and Institute for Research in Fundamental Sciences (IPM), Tehran, Iran) |
| title_fullStr | Durable phase-change memory architectures edited by Marjan Asadinia (University of Arkansas, Fayetteville, AR, United States), Hamid Sarbazi-Azad (Sharif University of Technology and Institute for Research in Fundamental Sciences (IPM), Tehran, Iran) |
| title_full_unstemmed | Durable phase-change memory architectures edited by Marjan Asadinia (University of Arkansas, Fayetteville, AR, United States), Hamid Sarbazi-Azad (Sharif University of Technology and Institute for Research in Fundamental Sciences (IPM), Tehran, Iran) |
| title_short | Durable phase-change memory architectures |
| title_sort | durable phase change memory architectures |
| topic | Hardware (DE-588)4023422-8 gnd |
| topic_facet | Hardware |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=032199622&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV002527667 |
| work_keys_str_mv | AT asadiniamarjan durablephasechangememoryarchitectures AT sarbaziazadhamid durablephasechangememoryarchitectures |