Verfügbarkeit: Algorithms and hardware for error correction coding with high coding gain

Algorithms and hardware for error correction coding with high coding gain: = Algorithmen und Hardware für Fehlerkorrekturverfahren mit hohem Codierungsgewinn

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Bibliographische Detailangaben
Beteilige Person:	Scholl, Stefan 1983- (VerfasserIn)
Format:	Hochschulschrift/Dissertation Buch
Sprache:	Deutsch
Veröffentlicht:	Kaiserslautern Technische Universität Kaiserslautern [2018]
Schriftenreihe:	Forschungsberichte Mikroelektronik Band 28
Schlagwörter:	Fehlerkorrekturcode Hochschulschrift
Links:	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=030588263&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
ISBN:	9783959740821

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Datensatz im Suchindex

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adam_text	CONTENTS 1 INTRODUCTION 1 1.1 MOTIVATION......................................................................................................... 1 1.2 CONTRIBUTION AND O U TLIN E ................................................................................ 4 1.3 FUNDAMENTALS OF COMMUNICATION S YSTEM S .................................................... 5 1.3.1 WHY ERROR CORRECTION CODING?........................................................... 5 1.3.2 TRANSMISSION S Y STEM .......................................................................... 7 1.3.3 DECODING STRATEGIES .......................................................................... 9 1.3.4 NON-BINARY CODES AND HIGHER-ORDER M ODULATION............................ 10 1.3.5 CLASSIC AND MODERN C O D E S................................................................. 11 2 INTEGER PROGRAMMING FORMULATIONS 15 2.1 BASIC MATHEMATICAL OPTIMIZATION T H E O R Y .................................................... 15 2.2 INTEGER PROGRAMMING FOR ML D E C O D IN G ........................................................ 16 2.2.1 FORMULATION ......................................................................................... 16 2.2.2 ANALYSIS OF ML VS HEURISTIC DECODING ........................................... 17 2.2.3 ANALYSIS OF BINARY VS NON-BINARY LDPC C O D ES ............................... 18 2.3 NEW FORMULATION FOR RELIABILITY BASED D E C O D IN G ........................................ 19 2.3.1 CHASE DECODING AND OSD ALGORITHM S .............................................. 19 2.3.2 FORMULATIONS FOR CHASE DECODING AND O S D ..................................... 20 2.4 MODELLING JOINT OPTIMAL DECODING AND DEMODULATION .................................. 21 3 ALGORITHMS FOR INTEGER PROGRAMMING BASED ML DECODING 25 3.1 INTRODUCTION TO LINEAR PROGRAMMING FOR DECODING........................................ 25 3.1.1 LINEAR PROGRAM M ING.......................................................................... 25 3.1.2 INTEGER LINEAR PROGRAM M ING.............................................................. 26 3.1.3 LINEAR PROGRAMMING DECODING AND FELDMANS R E LA X A TIO N .............. 28 3.1.4 ADAPTIVE LINEAR PROGRAMMING D E C O D IN G ........................................ 29 3.2 A NEW EFFICIENT ML DECODING A LG O RITH M ..................................................... 30 3.2.1 STATE-OF-THE-ART ALGORITHMS FOR ML D ECODING .................................. 31 3.2.2 TECHNIQUES FOR EFFICIENT BRANCH AND B O U N D ..................................... 31 3.2.3 ALGORITHM O V ERV IEW .......................................................................... 33 3.2.4 BRANCHING............................................................................................. 33 3.2.5 THE PROCESSING ORDER OF THE LIST L / NODE S E LE C TIO N ...................... 34 3.2.6 B OUNDING............................................................................................. 35 3.2.7 ADAPTIVE LP DECODING FOR LOWER B O U N D S ........................................ 35 3.2.8 HEURISTIC DECODING FOR UPPER B O U N D S............................................... 37 3.2.9 NUMERICAL R E S U LT S ............................................................................. 37 3.3 AN ADVANCED SIMPLEX ALGORITHM ................................................................. 38 3.3.1 STATE-OF-THE-ART LP SOLVERS .............................................................. 38 3.3.2 THE PRIMAL SIMPLEX ALGORITHM........................................................... 39 3.3.3 THE DUAL SIMPLEX ALGORITHM FOR D E C O D IN G ..................................... 41 3.3.4 ADAPTIVE LP DECODING WITH THE DUAL SIMPLEX ALGORITHM ................. 43 3.3.5 COMPLEXITY C OM PARISON.................................................................... 44 4 EFFICIENT SOFT DECISION DECODING FOR REED-SOLOMON CODES 47 4.1 STATE-OF-THE-ART SOFT DECISION D E C O D IN G ........................................................ 48 4.1.1 A LGO RITH M S.......................................................................................... 48 4.1.2 H ARDW ARE............................................................................................. 50 4.2 A NEW HARDWARE EFFICIENT A LG O RITH M ........................................................... 51 4.3 HARDWARE A RCH ITECTU RE.................................................................................... 54 4.3.1 S O R TIN G ................................................................................................ 57 4.3.2 SYNDROME CALCULATION AND W EIGHTING .............................................. 59 4.3.3 GAUSSIAN ELIMINATION.......................................................................... 61 4.3.4 PARITY CHECK MATRIX G ENERATION........................................................ 70 4.3.5 CORRECTION UNIT FOR ORDER-1 AND ORDER-2 R EPROCESSING ................... 75 4.4 DECODER DESIGN STUDIES ................................................................................... 76 4.4.1 A SOFT RS DECODER FOR HIGH T H RO U G H P U T......................................... 77 4.4.2 A SOFT RS DECODER FOR MODERATE THROUGHPUT .................................. 79 4.4.3 A SOFT RS DECODER FOR HIGH CODING G A IN ........................................ 80 4.4.4 COMPARISON OF THE STUDIES WITH STATE-OF-THE-ART ............................... 81 5 ADVANCED DECODER FOR LDPC CODES 83 5.1 STATE-OF-THE-ART DECODING FOR IMPROVED CODING G A I N .................................. 84 5.2 SATURATED MIN-SUM DECODING FOR HIGH CODING G A I N .................................. 84 5.2.1 THE SMS DECODING A LGORITHM ........................................................... 84 5.2.2 SERIAL SMS HARDWARE A RCHITECTURES.................................................. 86 5.2.3 PARALLEL SMS HARDWARE ARCHITECTURE .............................................. 89 5.2.4 LATENCY ANALYSIS AND STOPPING C RITE RIO N ........................................ 89 5.3 EFFICIENT AFTERBURNER* DECODING S C H E M E ..................................................... 91 5.3.1 DECODING SCHEME ............................................................................. 91 5.3.2 HARDWARE A RCHITECTURE....................................................................... 94 5.4 IMPLEMENTATION R ESULTS ................................................................................... 96 5.4.1 FRAME ERROR R A TE ................................................................................ 96 5.4.2 28 NM ASIC IMPLEMENTATION.............................................................. 97 5.5 AFTERBURNER DECODING AND DARK S ILIC O N ..................................................... 98 6 CONCLUSION 103 7 ZUSAMMENFASSUNG 105 A ML SIMULATION RESULTS 111 B SUM-PRODUCT ALGORITHM FOR DECODING LDPC CODES 117 BIBLIOGRAPHY 121 LIST OF FIGURES 131 LIST OF TABLES 135 LIST OF ALGORITHMS 137
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discipline	Elektrotechnik / Elektronik / Nachrichtentechnik
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indexdate	2024-12-20T18:20:35Z
institution	BVB
isbn	9783959740821
language	German
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publishDate	2018
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publisher	Technische Universität Kaiserslautern
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series	Forschungsberichte Mikroelektronik
series2	Forschungsberichte Mikroelektronik
spellingShingle	Scholl, Stefan 1983- Algorithms and hardware for error correction coding with high coding gain = Algorithmen und Hardware für Fehlerkorrekturverfahren mit hohem Codierungsgewinn Forschungsberichte Mikroelektronik Fehlerkorrekturcode (DE-588)4124917-3 gnd
subject_GND	(DE-588)4124917-3 (DE-588)4113937-9
title	Algorithms and hardware for error correction coding with high coding gain = Algorithmen und Hardware für Fehlerkorrekturverfahren mit hohem Codierungsgewinn
title_alt	Algorithmen und Hardware für Fehlerkorrekturverfahren mit hohem Codierungsgewinn
title_auth	Algorithms and hardware for error correction coding with high coding gain = Algorithmen und Hardware für Fehlerkorrekturverfahren mit hohem Codierungsgewinn
title_exact_search	Algorithms and hardware for error correction coding with high coding gain = Algorithmen und Hardware für Fehlerkorrekturverfahren mit hohem Codierungsgewinn
title_full	Algorithms and hardware for error correction coding with high coding gain = Algorithmen und Hardware für Fehlerkorrekturverfahren mit hohem Codierungsgewinn Stefan Scholl
title_fullStr	Algorithms and hardware for error correction coding with high coding gain = Algorithmen und Hardware für Fehlerkorrekturverfahren mit hohem Codierungsgewinn Stefan Scholl
title_full_unstemmed	Algorithms and hardware for error correction coding with high coding gain = Algorithmen und Hardware für Fehlerkorrekturverfahren mit hohem Codierungsgewinn Stefan Scholl
title_short	Algorithms and hardware for error correction coding with high coding gain
title_sort	algorithms and hardware for error correction coding with high coding gain algorithmen und hardware fur fehlerkorrekturverfahren mit hohem codierungsgewinn
title_sub	= Algorithmen und Hardware für Fehlerkorrekturverfahren mit hohem Codierungsgewinn
topic	Fehlerkorrekturcode (DE-588)4124917-3 gnd
topic_facet	Fehlerkorrekturcode Hochschulschrift
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=030588263&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
volume_link	(DE-604)BV012925671
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