Logic Minimization Algorithms for VLSI Synthesis:
The roots of the project which culminates with the writing of this book can be traced to the work on logic synthesis started in 1979 at the IBM Watson Research Center and at University of California, Berkeley. During the preliminary phases of these projects, the impor tance of logic minimization fo...
Gespeichert in:
| Beteiligte Personen: | , , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | Englisch |
| Veröffentlicht: |
Boston, MA
Springer US
1984
|
| Schriftenreihe: | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture, and Digital Signal Processing
2 |
| Schlagwörter: | |
| Links: | https://doi.org/10.1007/978-1-4613-2821-6 https://doi.org/10.1007/978-1-4613-2821-6 |
| Zusammenfassung: | The roots of the project which culminates with the writing of this book can be traced to the work on logic synthesis started in 1979 at the IBM Watson Research Center and at University of California, Berkeley. During the preliminary phases of these projects, the impor tance of logic minimization for the synthesis of area and performance effective circuits clearly emerged. In 1980, Richard Newton stirred our interest by pointing out new heuristic algorithms for two-level logic minimization and the potential for improving upon existing approaches. In the summer of 1981, the authors organized and participated in a seminar on logic manipulation at IBM Research. One of the goals of the seminar was to study the literature on logic minimization and to look at heuristic algorithms from a fundamental and comparative point of view. The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result. ESPRESSO-II was born and an APL implemen tation was created in the summer of 1982. The results of preliminary tests on a fairly large set of industrial examples were good enough to justify the publication of our algorithms. It is hoped that the strength and speed of our minimizer warrant its Italian name, which denotes both express delivery and a specially-brewed black coffee |
| Umfang: | 1 Online-Ressource (XII, 194 p) |
| ISBN: | 9781461328216 |
| DOI: | 10.1007/978-1-4613-2821-6 |
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| spelling | Brayton, Robert K. Verfasser aut Logic Minimization Algorithms for VLSI Synthesis by Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli Boston, MA Springer US 1984 1 Online-Ressource (XII, 194 p) txt rdacontent c rdamedia cr rdacarrier The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture, and Digital Signal Processing 2 The roots of the project which culminates with the writing of this book can be traced to the work on logic synthesis started in 1979 at the IBM Watson Research Center and at University of California, Berkeley. During the preliminary phases of these projects, the impor tance of logic minimization for the synthesis of area and performance effective circuits clearly emerged. In 1980, Richard Newton stirred our interest by pointing out new heuristic algorithms for two-level logic minimization and the potential for improving upon existing approaches. In the summer of 1981, the authors organized and participated in a seminar on logic manipulation at IBM Research. One of the goals of the seminar was to study the literature on logic minimization and to look at heuristic algorithms from a fundamental and comparative point of view. The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result. ESPRESSO-II was born and an APL implemen tation was created in the summer of 1982. The results of preliminary tests on a fairly large set of industrial examples were good enough to justify the publication of our algorithms. It is hoped that the strength and speed of our minimizer warrant its Italian name, which denotes both express delivery and a specially-brewed black coffee Computer Science Computer-Aided Engineering (CAD, CAE) and Design Computational Mathematics and Numerical Analysis Electrical Engineering Computer science Computer-aided engineering Computer mathematics Electrical engineering Synthese (DE-588)4418958-8 gnd rswk-swf Algorithmus (DE-588)4001183-5 gnd rswk-swf Minimierung (DE-588)4251074-0 gnd rswk-swf Optimierung (DE-588)4043664-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Synthese (DE-588)4418958-8 s Minimierung (DE-588)4251074-0 s Algorithmus (DE-588)4001183-5 s 1\p DE-604 Optimierung (DE-588)4043664-0 s 2\p DE-604 Hachtel, Gary D. aut McMullen, Curtis T. aut Sangiovanni-Vincentelli, Alberto L. aut Erscheint auch als Druck-Ausgabe 9781461297840 https://doi.org/10.1007/978-1-4613-2821-6 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Brayton, Robert K. Hachtel, Gary D. McMullen, Curtis T. Sangiovanni-Vincentelli, Alberto L. Logic Minimization Algorithms for VLSI Synthesis Computer Science Computer-Aided Engineering (CAD, CAE) and Design Computational Mathematics and Numerical Analysis Electrical Engineering Computer science Computer-aided engineering Computer mathematics Electrical engineering Synthese (DE-588)4418958-8 gnd Algorithmus (DE-588)4001183-5 gnd Minimierung (DE-588)4251074-0 gnd Optimierung (DE-588)4043664-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4418958-8 (DE-588)4001183-5 (DE-588)4251074-0 (DE-588)4043664-0 (DE-588)4117388-0 |
| title | Logic Minimization Algorithms for VLSI Synthesis |
| title_auth | Logic Minimization Algorithms for VLSI Synthesis |
| title_exact_search | Logic Minimization Algorithms for VLSI Synthesis |
| title_full | Logic Minimization Algorithms for VLSI Synthesis by Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli |
| title_fullStr | Logic Minimization Algorithms for VLSI Synthesis by Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli |
| title_full_unstemmed | Logic Minimization Algorithms for VLSI Synthesis by Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli |
| title_short | Logic Minimization Algorithms for VLSI Synthesis |
| title_sort | logic minimization algorithms for vlsi synthesis |
| topic | Computer Science Computer-Aided Engineering (CAD, CAE) and Design Computational Mathematics and Numerical Analysis Electrical Engineering Computer science Computer-aided engineering Computer mathematics Electrical engineering Synthese (DE-588)4418958-8 gnd Algorithmus (DE-588)4001183-5 gnd Minimierung (DE-588)4251074-0 gnd Optimierung (DE-588)4043664-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Computer Science Computer-Aided Engineering (CAD, CAE) and Design Computational Mathematics and Numerical Analysis Electrical Engineering Computer science Computer-aided engineering Computer mathematics Electrical engineering Synthese Algorithmus Minimierung Optimierung VLSI |
| url | https://doi.org/10.1007/978-1-4613-2821-6 |
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