Sequential Logic Synthesis:
3. 2 Input Encoding Targeting Two-Level Logic . . . . . . . . 27 3. 2. 1 One-Hot Coding and Multiple-Valued Minimization 28 3. 2. 2 Input Constraints and Face Embedding 30 3. 3 Satisfying Encoding Constraints . . . . . . . 32 3. 3. 1 Definitions . . . . . . . . . . . . . . . 32 3. 3. 2 Column-Based...
Gespeichert in:
| Beteiligte Personen: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | Englisch |
| Veröffentlicht: |
Boston, MA
Springer US
1992
|
| Schriftenreihe: | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
162 |
| Schlagwörter: | |
| Links: | https://doi.org/10.1007/978-1-4615-3628-4 https://doi.org/10.1007/978-1-4615-3628-4 |
| Zusammenfassung: | 3. 2 Input Encoding Targeting Two-Level Logic . . . . . . . . 27 3. 2. 1 One-Hot Coding and Multiple-Valued Minimization 28 3. 2. 2 Input Constraints and Face Embedding 30 3. 3 Satisfying Encoding Constraints . . . . . . . 32 3. 3. 1 Definitions . . . . . . . . . . . . . . . 32 3. 3. 2 Column-Based Constraint Satisfaction 33 3. 3. 3 Row-Based Constraint Satisfaction . . 37 3. 3. 4 Constraint Satisfaction Using Dichotomies . 38 3. 3. 5 Simulated Annealing for Constraint Satisfaction 41 3. 4 Input Encoding Targeting Multilevel Logic. . 43 3. 4. 1 Kernels and Kernel Intersections . . . 44 3. 4. 2 Kernels and Multiple-Valued Variables 46 3. 4. 3 Multiple-Valued Factorization. . . . . 48 3. 4. 4 Size Estimation in Algebraic Decomposition . 53 3. 4. 5 The Encoding Step . 54 3. 5 Conclusion . . . . . . . . . 55 4 Encoding of Symbolic Outputs 57 4. 1 Heuristic Output Encoding Targeting Two-Level Logic. 59 4. 1. 1 Dominance Relations. . . . . . . . . . . . . . . . 59 4. 1. 2 Output Encoding by the Derivation of Dominance Relations . . . . . . . . . . . . . . . . . . . . . 60 . . 4. 1. 3 Heuristics to Minimize the Number of Encoding Bits . . . . . . . . . . . . 64 4. 1. 4 Disjunctive Relationships . . . . . . . . . . . 65 4. 1. 5 Summary . . . . . . . . . . . . . . . . . . 66 . . 4. 2 Exact Output Encoding Targeting Two-Level Logic. 66 4. 2. 1 Generation of Generalized Prime Implicants . 68 4. 2. 2 Selecting a Minimum Encodeable Cover . . . 68 4. 2. 3 Dominance and Disjunctive Relationships to S- isfy Constraints . . . . . . . . . . . 70 4. 2. 4 Constructing the Optimized Cover 73 4. 2. 5 Correctness of the Procedure . . 73 4. 2. 6 Multiple Symbolic Outputs . . |
| Umfang: | 1 Online-Ressource (XX, 225 p) |
| ISBN: | 9781461536284 |
| DOI: | 10.1007/978-1-4615-3628-4 |
Internformat
MARC
| LEADER | 00000nam a2200000zcb4500 | ||
|---|---|---|---|
| 001 | BV045186225 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 180912s1992 xx o|||| 00||| eng d | ||
| 020 | |a 9781461536284 |9 978-1-4615-3628-4 | ||
| 024 | 7 | |a 10.1007/978-1-4615-3628-4 |2 doi | |
| 035 | |a (ZDB-2-ENG)978-1-4615-3628-4 | ||
| 035 | |a (OCoLC)1184450242 | ||
| 035 | |a (DE-599)BVBBV045186225 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-634 | ||
| 082 | 0 | |a 621.3815 |2 23 | |
| 100 | 1 | |a Ashar, Pranav |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Sequential Logic Synthesis |c by Pranav Ashar, Srinivas Devadas, A. Richard Newton |
| 264 | 1 | |a Boston, MA |b Springer US |c 1992 | |
| 300 | |a 1 Online-Ressource (XX, 225 p) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |v 162 | |
| 520 | |a 3. 2 Input Encoding Targeting Two-Level Logic . . . . . . . . 27 3. 2. 1 One-Hot Coding and Multiple-Valued Minimization 28 3. 2. 2 Input Constraints and Face Embedding 30 3. 3 Satisfying Encoding Constraints . . . . . . . 32 3. 3. 1 Definitions . . . . . . . . . . . . . . . 32 3. 3. 2 Column-Based Constraint Satisfaction 33 3. 3. 3 Row-Based Constraint Satisfaction . . 37 3. 3. 4 Constraint Satisfaction Using Dichotomies . 38 3. 3. 5 Simulated Annealing for Constraint Satisfaction 41 3. 4 Input Encoding Targeting Multilevel Logic. . 43 3. 4. 1 Kernels and Kernel Intersections . . . 44 3. 4. 2 Kernels and Multiple-Valued Variables 46 3. 4. 3 Multiple-Valued Factorization. . . . . 48 3. 4. 4 Size Estimation in Algebraic Decomposition . 53 3. 4. 5 The Encoding Step . 54 3. 5 Conclusion . . . . . . . . . 55 4 Encoding of Symbolic Outputs 57 4. 1 Heuristic Output Encoding Targeting Two-Level Logic. 59 4. 1. 1 Dominance Relations. . . . . . . . . . . . . . . . 59 4. 1. 2 Output Encoding by the Derivation of Dominance Relations . . . . . . . . . . . . . . . . . . . . . 60 . . 4. 1. 3 Heuristics to Minimize the Number of Encoding Bits . . . . . . . . . . . . 64 4. 1. 4 Disjunctive Relationships . . . . . . . . . . . 65 4. 1. 5 Summary . . . . . . . . . . . . . . . . . . 66 . . 4. 2 Exact Output Encoding Targeting Two-Level Logic. 66 4. 2. 1 Generation of Generalized Prime Implicants . 68 4. 2. 2 Selecting a Minimum Encodeable Cover . . . 68 4. 2. 3 Dominance and Disjunctive Relationships to S- isfy Constraints . . . . . . . . . . . 70 4. 2. 4 Constructing the Optimized Cover 73 4. 2. 5 Correctness of the Procedure . . 73 4. 2. 6 Multiple Symbolic Outputs . . | ||
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Circuits and Systems | |
| 650 | 4 | |a Electrical Engineering | |
| 650 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design | |
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Computer-aided engineering | |
| 650 | 4 | |a Electrical engineering | |
| 650 | 4 | |a Electronic circuits | |
| 650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Schaltwerk |0 (DE-588)4052057-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Datenverarbeitung |0 (DE-588)4011152-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CAD |0 (DE-588)4069794-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Automatentheorie |0 (DE-588)4003953-5 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Datenverarbeitung |0 (DE-588)4011152-0 |D s |
| 689 | 0 | 1 | |a Logischer Entwurf |0 (DE-588)4168051-0 |D s |
| 689 | 0 | 2 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 689 | 1 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 1 | 1 | |a CAD |0 (DE-588)4069794-0 |D s |
| 689 | 1 | |8 2\p |5 DE-604 | |
| 689 | 2 | 0 | |a Schaltwerk |0 (DE-588)4052057-2 |D s |
| 689 | 2 | |8 3\p |5 DE-604 | |
| 689 | 3 | 0 | |a Automatentheorie |0 (DE-588)4003953-5 |D s |
| 689 | 3 | |8 4\p |5 DE-604 | |
| 700 | 1 | |a Devadas, Srinivas |4 aut | |
| 700 | 1 | |a Newton, A. Richard |4 aut | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781461366133 |
| 856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4615-3628-4 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-2-ENG | ||
| 940 | 1 | |q ZDB-2-ENG_Archiv | |
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 4\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-030575402 | |
| 966 | e | |u https://doi.org/10.1007/978-1-4615-3628-4 |l DE-634 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1818984512264077312 |
|---|---|
| any_adam_object | |
| author | Ashar, Pranav Devadas, Srinivas Newton, A. Richard |
| author_facet | Ashar, Pranav Devadas, Srinivas Newton, A. Richard |
| author_role | aut aut aut |
| author_sort | Ashar, Pranav |
| author_variant | p a pa s d sd a r n ar arn |
| building | Verbundindex |
| bvnumber | BV045186225 |
| collection | ZDB-2-ENG |
| ctrlnum | (ZDB-2-ENG)978-1-4615-3628-4 (OCoLC)1184450242 (DE-599)BVBBV045186225 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4615-3628-4 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>04633nam a2200745zcb4500</leader><controlfield tag="001">BV045186225</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180912s1992 xx o|||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781461536284</subfield><subfield code="9">978-1-4615-3628-4</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4615-3628-4</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4615-3628-4</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1184450242</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045186225</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Ashar, Pranav</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Sequential Logic Synthesis</subfield><subfield code="c">by Pranav Ashar, Srinivas Devadas, A. Richard Newton</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">1992</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XX, 225 p)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing</subfield><subfield code="v">162</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">3. 2 Input Encoding Targeting Two-Level Logic . . . . . . . . 27 3. 2. 1 One-Hot Coding and Multiple-Valued Minimization 28 3. 2. 2 Input Constraints and Face Embedding 30 3. 3 Satisfying Encoding Constraints . . . . . . . 32 3. 3. 1 Definitions . . . . . . . . . . . . . . . 32 3. 3. 2 Column-Based Constraint Satisfaction 33 3. 3. 3 Row-Based Constraint Satisfaction . . 37 3. 3. 4 Constraint Satisfaction Using Dichotomies . 38 3. 3. 5 Simulated Annealing for Constraint Satisfaction 41 3. 4 Input Encoding Targeting Multilevel Logic. . 43 3. 4. 1 Kernels and Kernel Intersections . . . 44 3. 4. 2 Kernels and Multiple-Valued Variables 46 3. 4. 3 Multiple-Valued Factorization. . . . . 48 3. 4. 4 Size Estimation in Algebraic Decomposition . 53 3. 4. 5 The Encoding Step . 54 3. 5 Conclusion . . . . . . . . . 55 4 Encoding of Symbolic Outputs 57 4. 1 Heuristic Output Encoding Targeting Two-Level Logic. 59 4. 1. 1 Dominance Relations. . . . . . . . . . . . . . . . 59 4. 1. 2 Output Encoding by the Derivation of Dominance Relations . . . . . . . . . . . . . . . . . . . . . 60 . . 4. 1. 3 Heuristics to Minimize the Number of Encoding Bits . . . . . . . . . . . . 64 4. 1. 4 Disjunctive Relationships . . . . . . . . . . . 65 4. 1. 5 Summary . . . . . . . . . . . . . . . . . . 66 . . 4. 2 Exact Output Encoding Targeting Two-Level Logic. 66 4. 2. 1 Generation of Generalized Prime Implicants . 68 4. 2. 2 Selecting a Minimum Encodeable Cover . . . 68 4. 2. 3 Dominance and Disjunctive Relationships to S- isfy Constraints . . . . . . . . . . . 70 4. 2. 4 Constructing the Optimized Cover 73 4. 2. 5 Correctness of the Procedure . . 73 4. 2. 6 Multiple Symbolic Outputs . .</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-Aided Engineering (CAD, CAE) and Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-aided engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltwerk</subfield><subfield code="0">(DE-588)4052057-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Datenverarbeitung</subfield><subfield code="0">(DE-588)4011152-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Automatentheorie</subfield><subfield code="0">(DE-588)4003953-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Datenverarbeitung</subfield><subfield code="0">(DE-588)4011152-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Schaltwerk</subfield><subfield code="0">(DE-588)4052057-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="8">3\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="3" ind2="0"><subfield code="a">Automatentheorie</subfield><subfield code="0">(DE-588)4003953-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2=" "><subfield code="8">4\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Devadas, Srinivas</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Newton, A. Richard</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781461366133</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4615-3628-4</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_Archiv</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">3\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">4\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030575402</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4615-3628-4</subfield><subfield code="l">DE-634</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV045186225 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T18:20:11Z |
| institution | BVB |
| isbn | 9781461536284 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030575402 |
| oclc_num | 1184450242 |
| open_access_boolean | |
| owner | DE-634 |
| owner_facet | DE-634 |
| physical | 1 Online-Ressource (XX, 225 p) |
| psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| publisher | Springer US |
| record_format | marc |
| series2 | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
| spelling | Ashar, Pranav Verfasser aut Sequential Logic Synthesis by Pranav Ashar, Srinivas Devadas, A. Richard Newton Boston, MA Springer US 1992 1 Online-Ressource (XX, 225 p) txt rdacontent c rdamedia cr rdacarrier The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 162 3. 2 Input Encoding Targeting Two-Level Logic . . . . . . . . 27 3. 2. 1 One-Hot Coding and Multiple-Valued Minimization 28 3. 2. 2 Input Constraints and Face Embedding 30 3. 3 Satisfying Encoding Constraints . . . . . . . 32 3. 3. 1 Definitions . . . . . . . . . . . . . . . 32 3. 3. 2 Column-Based Constraint Satisfaction 33 3. 3. 3 Row-Based Constraint Satisfaction . . 37 3. 3. 4 Constraint Satisfaction Using Dichotomies . 38 3. 3. 5 Simulated Annealing for Constraint Satisfaction 41 3. 4 Input Encoding Targeting Multilevel Logic. . 43 3. 4. 1 Kernels and Kernel Intersections . . . 44 3. 4. 2 Kernels and Multiple-Valued Variables 46 3. 4. 3 Multiple-Valued Factorization. . . . . 48 3. 4. 4 Size Estimation in Algebraic Decomposition . 53 3. 4. 5 The Encoding Step . 54 3. 5 Conclusion . . . . . . . . . 55 4 Encoding of Symbolic Outputs 57 4. 1 Heuristic Output Encoding Targeting Two-Level Logic. 59 4. 1. 1 Dominance Relations. . . . . . . . . . . . . . . . 59 4. 1. 2 Output Encoding by the Derivation of Dominance Relations . . . . . . . . . . . . . . . . . . . . . 60 . . 4. 1. 3 Heuristics to Minimize the Number of Encoding Bits . . . . . . . . . . . . 64 4. 1. 4 Disjunctive Relationships . . . . . . . . . . . 65 4. 1. 5 Summary . . . . . . . . . . . . . . . . . . 66 . . 4. 2 Exact Output Encoding Targeting Two-Level Logic. 66 4. 2. 1 Generation of Generalized Prime Implicants . 68 4. 2. 2 Selecting a Minimum Encodeable Cover . . . 68 4. 2. 3 Dominance and Disjunctive Relationships to S- isfy Constraints . . . . . . . . . . . 70 4. 2. 4 Constructing the Optimized Cover 73 4. 2. 5 Correctness of the Procedure . . 73 4. 2. 6 Multiple Symbolic Outputs . . Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Schaltwerk (DE-588)4052057-2 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Datenverarbeitung (DE-588)4011152-0 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf Automatentheorie (DE-588)4003953-5 gnd rswk-swf Datenverarbeitung (DE-588)4011152-0 s Logischer Entwurf (DE-588)4168051-0 s VLSI (DE-588)4117388-0 s 1\p DE-604 CAD (DE-588)4069794-0 s 2\p DE-604 Schaltwerk (DE-588)4052057-2 s 3\p DE-604 Automatentheorie (DE-588)4003953-5 s 4\p DE-604 Devadas, Srinivas aut Newton, A. Richard aut Erscheint auch als Druck-Ausgabe 9781461366133 https://doi.org/10.1007/978-1-4615-3628-4 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Ashar, Pranav Devadas, Srinivas Newton, A. Richard Sequential Logic Synthesis Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Logischer Entwurf (DE-588)4168051-0 gnd Schaltwerk (DE-588)4052057-2 gnd VLSI (DE-588)4117388-0 gnd Datenverarbeitung (DE-588)4011152-0 gnd CAD (DE-588)4069794-0 gnd Automatentheorie (DE-588)4003953-5 gnd |
| subject_GND | (DE-588)4168051-0 (DE-588)4052057-2 (DE-588)4117388-0 (DE-588)4011152-0 (DE-588)4069794-0 (DE-588)4003953-5 |
| title | Sequential Logic Synthesis |
| title_auth | Sequential Logic Synthesis |
| title_exact_search | Sequential Logic Synthesis |
| title_full | Sequential Logic Synthesis by Pranav Ashar, Srinivas Devadas, A. Richard Newton |
| title_fullStr | Sequential Logic Synthesis by Pranav Ashar, Srinivas Devadas, A. Richard Newton |
| title_full_unstemmed | Sequential Logic Synthesis by Pranav Ashar, Srinivas Devadas, A. Richard Newton |
| title_short | Sequential Logic Synthesis |
| title_sort | sequential logic synthesis |
| topic | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Logischer Entwurf (DE-588)4168051-0 gnd Schaltwerk (DE-588)4052057-2 gnd VLSI (DE-588)4117388-0 gnd Datenverarbeitung (DE-588)4011152-0 gnd CAD (DE-588)4069794-0 gnd Automatentheorie (DE-588)4003953-5 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Logischer Entwurf Schaltwerk VLSI Datenverarbeitung CAD Automatentheorie |
| url | https://doi.org/10.1007/978-1-4615-3628-4 |
| work_keys_str_mv | AT asharpranav sequentiallogicsynthesis AT devadassrinivas sequentiallogicsynthesis AT newtonarichard sequentiallogicsynthesis |