The Designer’s Guide to Verilog-AMS, June 2004:
The Verilog Hardware Description Language (Verilog-HDL) has long been the most popular language for describing complex digital hardware. It started life as a prop- etary language but was donated by Cadence Design Systems to the design community to serve as the basis of an open standard. That standar...
Gespeichert in:
| Beteiligte Personen: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | Englisch |
| Veröffentlicht: |
Boston, MA
Springer US
2004
|
| Schriftenreihe: | The Designer’s Guide Book Series
|
| Schlagwörter: | |
| Links: | https://doi.org/10.1007/b117108 https://doi.org/10.1007/b117108 https://doi.org/10.1007/b117108 |
| Zusammenfassung: | The Verilog Hardware Description Language (Verilog-HDL) has long been the most popular language for describing complex digital hardware. It started life as a prop- etary language but was donated by Cadence Design Systems to the design community to serve as the basis of an open standard. That standard was formalized in 1995 by the IEEE in standard 1364-1995. About that same time a group named Analog Verilog International formed with the intent of proposing extensions to Verilog to support analog and mixed-signal simulation. The first fruits of the labor of that group became available in 1996 when the language definition of Verilog-A was released. Verilog-A was not intended to work directly with Verilog-HDL. Rather it was a language with Similar syntax and related semantics that was intended to model analog systems and be compatible with SPICE-class circuit simulation engines. The first implementation of Verilog-A soon followed: a version from Cadence that ran on their Spectre circuit simulator. As more implementations of Verilog-A became available, the group defining the a- log and mixed-signal extensions to Verilog continued their work, releasing the defi- tion of Verilog-AMS in 2000. Verilog-AMS combines both Verilog-HDL and Verilog-A, and adds additional mixed-signal constructs, providing a hardware description language suitable for analog, digital, and mixed-signal systems. Again, Cadence was first to release an implementation of this new language, in a product named AMS Designer that combines their Verilog and Spectre simulation engines |
| Umfang: | 1 Online-Ressource (XII, 270 p) |
| ISBN: | 9781402080456 |
| DOI: | 10.1007/b117108 |
Internformat
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV045148670 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 180827s2004 xx o|||| 00||| eng d | ||
| 020 | |a 9781402080456 |9 978-1-4020-8045-6 | ||
| 024 | 7 | |a 10.1007/b117108 |2 doi | |
| 035 | |a (ZDB-2-ENG)978-1-4020-8045-6 | ||
| 035 | |a (OCoLC)1050950702 | ||
| 035 | |a (DE-599)BVBBV045148670 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-573 |a DE-634 | ||
| 082 | 0 | |a 621.3815 |2 23 | |
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 084 | |a ZN 4904 |0 (DE-625)157419: |2 rvk | ||
| 100 | 1 | |a Kundert, Kenneth S. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a The Designer’s Guide to Verilog-AMS, June 2004 |c by Kenneth S. Kundert, Olaf Zinke |
| 264 | 1 | |a Boston, MA |b Springer US |c 2004 | |
| 300 | |a 1 Online-Ressource (XII, 270 p) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a The Designer’s Guide Book Series | |
| 520 | |a The Verilog Hardware Description Language (Verilog-HDL) has long been the most popular language for describing complex digital hardware. It started life as a prop- etary language but was donated by Cadence Design Systems to the design community to serve as the basis of an open standard. That standard was formalized in 1995 by the IEEE in standard 1364-1995. About that same time a group named Analog Verilog International formed with the intent of proposing extensions to Verilog to support analog and mixed-signal simulation. The first fruits of the labor of that group became available in 1996 when the language definition of Verilog-A was released. Verilog-A was not intended to work directly with Verilog-HDL. Rather it was a language with Similar syntax and related semantics that was intended to model analog systems and be compatible with SPICE-class circuit simulation engines. The first implementation of Verilog-A soon followed: a version from Cadence that ran on their Spectre circuit simulator. As more implementations of Verilog-A became available, the group defining the a- log and mixed-signal extensions to Verilog continued their work, releasing the defi- tion of Verilog-AMS in 2000. Verilog-AMS combines both Verilog-HDL and Verilog-A, and adds additional mixed-signal constructs, providing a hardware description language suitable for analog, digital, and mixed-signal systems. Again, Cadence was first to release an implementation of this new language, in a product named AMS Designer that combines their Verilog and Spectre simulation engines | ||
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Circuits and Systems | |
| 650 | 4 | |a Electrical Engineering | |
| 650 | 4 | |a Computer Hardware | |
| 650 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design | |
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Computer hardware | |
| 650 | 4 | |a Computer-aided engineering | |
| 650 | 4 | |a Electrical engineering | |
| 650 | 4 | |a Electronic circuits | |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Mixed-Signal-Schaltung |0 (DE-588)4756481-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Computersimulation |0 (DE-588)4148259-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Mixed-Signal-Schaltung |0 (DE-588)4756481-7 |D s |
| 689 | 0 | 1 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 0 | 2 | |a Computersimulation |0 (DE-588)4148259-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 1 | |5 DE-604 | |
| 700 | 1 | |a Zinke, Olaf |4 aut | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781402080449 |
| 856 | 4 | 0 | |u https://doi.org/10.1007/b117108 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-2-ENG | ||
| 940 | 1 | |q ZDB-2-ENG_2000/2004 | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-030538369 | |
| 966 | e | |u https://doi.org/10.1007/b117108 |l DE-573 |p ZDB-2-ENG |q ZDB-2-ENG_2000/2004 |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/b117108 |l DE-634 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1818984457475981312 |
|---|---|
| any_adam_object | |
| author | Kundert, Kenneth S. Zinke, Olaf |
| author_facet | Kundert, Kenneth S. Zinke, Olaf |
| author_role | aut aut |
| author_sort | Kundert, Kenneth S. |
| author_variant | k s k ks ksk o z oz |
| building | Verbundindex |
| bvnumber | BV045148670 |
| classification_rvk | ST 250 ZN 4904 |
| collection | ZDB-2-ENG |
| ctrlnum | (ZDB-2-ENG)978-1-4020-8045-6 (OCoLC)1050950702 (DE-599)BVBBV045148670 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/b117108 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03998nam a2200661zc 4500</leader><controlfield tag="001">BV045148670</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180827s2004 xx o|||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781402080456</subfield><subfield code="9">978-1-4020-8045-6</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/b117108</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4020-8045-6</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1050950702</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045148670</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-573</subfield><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 250</subfield><subfield code="0">(DE-625)143626:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4904</subfield><subfield code="0">(DE-625)157419:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kundert, Kenneth S.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">The Designer’s Guide to Verilog-AMS, June 2004</subfield><subfield code="c">by Kenneth S. Kundert, Olaf Zinke</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">2004</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XII, 270 p)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">The Designer’s Guide Book Series</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">The Verilog Hardware Description Language (Verilog-HDL) has long been the most popular language for describing complex digital hardware. It started life as a prop- etary language but was donated by Cadence Design Systems to the design community to serve as the basis of an open standard. That standard was formalized in 1995 by the IEEE in standard 1364-1995. About that same time a group named Analog Verilog International formed with the intent of proposing extensions to Verilog to support analog and mixed-signal simulation. The first fruits of the labor of that group became available in 1996 when the language definition of Verilog-A was released. Verilog-A was not intended to work directly with Verilog-HDL. Rather it was a language with Similar syntax and related semantics that was intended to model analog systems and be compatible with SPICE-class circuit simulation engines. The first implementation of Verilog-A soon followed: a version from Cadence that ran on their Spectre circuit simulator. As more implementations of Verilog-A became available, the group defining the a- log and mixed-signal extensions to Verilog continued their work, releasing the defi- tion of Verilog-AMS in 2000. Verilog-AMS combines both Verilog-HDL and Verilog-A, and adds additional mixed-signal constructs, providing a hardware description language suitable for analog, digital, and mixed-signal systems. Again, Cadence was first to release an implementation of this new language, in a product named AMS Designer that combines their Verilog and Spectre simulation engines</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer Hardware</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-Aided Engineering (CAD, CAE) and Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer hardware</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-aided engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mixed-Signal-Schaltung</subfield><subfield code="0">(DE-588)4756481-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Computersimulation</subfield><subfield code="0">(DE-588)4148259-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Mixed-Signal-Schaltung</subfield><subfield code="0">(DE-588)4756481-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Computersimulation</subfield><subfield code="0">(DE-588)4148259-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Zinke, Olaf</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781402080449</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/b117108</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_2000/2004</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030538369</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/b117108</subfield><subfield code="l">DE-573</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_2000/2004</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/b117108</subfield><subfield code="l">DE-634</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV045148670 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T18:19:18Z |
| institution | BVB |
| isbn | 9781402080456 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030538369 |
| oclc_num | 1050950702 |
| open_access_boolean | |
| owner | DE-573 DE-634 |
| owner_facet | DE-573 DE-634 |
| physical | 1 Online-Ressource (XII, 270 p) |
| psigel | ZDB-2-ENG ZDB-2-ENG_2000/2004 ZDB-2-ENG ZDB-2-ENG_2000/2004 ZDB-2-ENG ZDB-2-ENG_Archiv |
| publishDate | 2004 |
| publishDateSearch | 2004 |
| publishDateSort | 2004 |
| publisher | Springer US |
| record_format | marc |
| series2 | The Designer’s Guide Book Series |
| spelling | Kundert, Kenneth S. Verfasser aut The Designer’s Guide to Verilog-AMS, June 2004 by Kenneth S. Kundert, Olaf Zinke Boston, MA Springer US 2004 1 Online-Ressource (XII, 270 p) txt rdacontent c rdamedia cr rdacarrier The Designer’s Guide Book Series The Verilog Hardware Description Language (Verilog-HDL) has long been the most popular language for describing complex digital hardware. It started life as a prop- etary language but was donated by Cadence Design Systems to the design community to serve as the basis of an open standard. That standard was formalized in 1995 by the IEEE in standard 1364-1995. About that same time a group named Analog Verilog International formed with the intent of proposing extensions to Verilog to support analog and mixed-signal simulation. The first fruits of the labor of that group became available in 1996 when the language definition of Verilog-A was released. Verilog-A was not intended to work directly with Verilog-HDL. Rather it was a language with Similar syntax and related semantics that was intended to model analog systems and be compatible with SPICE-class circuit simulation engines. The first implementation of Verilog-A soon followed: a version from Cadence that ran on their Spectre circuit simulator. As more implementations of Verilog-A became available, the group defining the a- log and mixed-signal extensions to Verilog continued their work, releasing the defi- tion of Verilog-AMS in 2000. Verilog-AMS combines both Verilog-HDL and Verilog-A, and adds additional mixed-signal constructs, providing a hardware description language suitable for analog, digital, and mixed-signal systems. Again, Cadence was first to release an implementation of this new language, in a product named AMS Designer that combines their Verilog and Spectre simulation engines Engineering Circuits and Systems Electrical Engineering Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Computer hardware Computer-aided engineering Electrical engineering Electronic circuits VERILOG (DE-588)4268385-3 gnd rswk-swf Mixed-Signal-Schaltung (DE-588)4756481-7 gnd rswk-swf Computersimulation (DE-588)4148259-1 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Mixed-Signal-Schaltung (DE-588)4756481-7 s Schaltungsentwurf (DE-588)4179389-4 s Computersimulation (DE-588)4148259-1 s DE-604 VERILOG (DE-588)4268385-3 s Zinke, Olaf aut Erscheint auch als Druck-Ausgabe 9781402080449 https://doi.org/10.1007/b117108 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Kundert, Kenneth S. Zinke, Olaf The Designer’s Guide to Verilog-AMS, June 2004 Engineering Circuits and Systems Electrical Engineering Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Computer hardware Computer-aided engineering Electrical engineering Electronic circuits VERILOG (DE-588)4268385-3 gnd Mixed-Signal-Schaltung (DE-588)4756481-7 gnd Computersimulation (DE-588)4148259-1 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| subject_GND | (DE-588)4268385-3 (DE-588)4756481-7 (DE-588)4148259-1 (DE-588)4179389-4 |
| title | The Designer’s Guide to Verilog-AMS, June 2004 |
| title_auth | The Designer’s Guide to Verilog-AMS, June 2004 |
| title_exact_search | The Designer’s Guide to Verilog-AMS, June 2004 |
| title_full | The Designer’s Guide to Verilog-AMS, June 2004 by Kenneth S. Kundert, Olaf Zinke |
| title_fullStr | The Designer’s Guide to Verilog-AMS, June 2004 by Kenneth S. Kundert, Olaf Zinke |
| title_full_unstemmed | The Designer’s Guide to Verilog-AMS, June 2004 by Kenneth S. Kundert, Olaf Zinke |
| title_short | The Designer’s Guide to Verilog-AMS, June 2004 |
| title_sort | the designer s guide to verilog ams june 2004 |
| topic | Engineering Circuits and Systems Electrical Engineering Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Computer hardware Computer-aided engineering Electrical engineering Electronic circuits VERILOG (DE-588)4268385-3 gnd Mixed-Signal-Schaltung (DE-588)4756481-7 gnd Computersimulation (DE-588)4148259-1 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Computer hardware Computer-aided engineering Electrical engineering Electronic circuits VERILOG Mixed-Signal-Schaltung Computersimulation Schaltungsentwurf |
| url | https://doi.org/10.1007/b117108 |
| work_keys_str_mv | AT kundertkenneths thedesignersguidetoverilogamsjune2004 AT zinkeolaf thedesignersguidetoverilogamsjune2004 |