Designing digital computing systems with Verilog:
This book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and st...
Gespeichert in:
| Beteilige Person: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | Englisch |
| Veröffentlicht: |
Cambridge
Cambridge University Press
2005
|
| Schlagwörter: | |
| Links: | https://doi.org/10.1017/CBO9780511607059 https://doi.org/10.1017/CBO9780511607059 https://doi.org/10.1017/CBO9780511607059 |
| Zusammenfassung: | This book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioural and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers |
| Beschreibung: | Title from publisher's bibliographic system (viewed on 05 Oct 2015) |
| Umfang: | 1 online resource (ix, 160 pages) |
| ISBN: | 9780511607059 |
| DOI: | 10.1017/CBO9780511607059 |
Internformat
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV043943312 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 161206s2005 xx o|||| 00||| eng d | ||
| 020 | |a 9780511607059 |c Online |9 978-0-511-60705-9 | ||
| 024 | 7 | |a 10.1017/CBO9780511607059 |2 doi | |
| 035 | |a (ZDB-20-CBO)CR9780511607059 | ||
| 035 | |a (OCoLC)850830959 | ||
| 035 | |a (DE-599)BVBBV043943312 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-12 |a DE-92 | ||
| 082 | 0 | |a 621.39/2 |2 22 | |
| 084 | |a ST 150 |0 (DE-625)143594: |2 rvk | ||
| 100 | 1 | |a Lilja, David J. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Designing digital computing systems with Verilog |c David J. Lilja and Sachin S. Sapatnekar |
| 264 | 1 | |a Cambridge |b Cambridge University Press |c 2005 | |
| 300 | |a 1 online resource (ix, 160 pages) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Title from publisher's bibliographic system (viewed on 05 Oct 2015) | ||
| 520 | |a This book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioural and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers | ||
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 650 | 4 | |a Electronic digital computers / Design and construction | |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Sapatnekar, Sachin S. |d 1967- |e Sonstige |4 oth | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druckausgabe |z 978-0-521-04572-8 |
| 776 | 0 | 8 | |i Erscheint auch als |n Druckausgabe |z 978-0-521-82866-6 |
| 856 | 4 | 0 | |u https://doi.org/10.1017/CBO9780511607059 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-20-CBO | ||
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-029352282 | |
| 966 | e | |u https://doi.org/10.1017/CBO9780511607059 |l DE-12 |p ZDB-20-CBO |q BSB_PDA_CBO |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1017/CBO9780511607059 |l DE-92 |p ZDB-20-CBO |q FHN_PDA_CBO |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1818982571988484096 |
|---|---|
| any_adam_object | |
| author | Lilja, David J. |
| author_facet | Lilja, David J. |
| author_role | aut |
| author_sort | Lilja, David J. |
| author_variant | d j l dj djl |
| building | Verbundindex |
| bvnumber | BV043943312 |
| classification_rvk | ST 150 |
| collection | ZDB-20-CBO |
| ctrlnum | (ZDB-20-CBO)CR9780511607059 (OCoLC)850830959 (DE-599)BVBBV043943312 |
| dewey-full | 621.39/2 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/2 |
| dewey-search | 621.39/2 |
| dewey-sort | 3621.39 12 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1017/CBO9780511607059 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02799nam a2200469zc 4500</leader><controlfield tag="001">BV043943312</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">161206s2005 xx o|||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780511607059</subfield><subfield code="c">Online</subfield><subfield code="9">978-0-511-60705-9</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1017/CBO9780511607059</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-20-CBO)CR9780511607059</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)850830959</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV043943312</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-12</subfield><subfield code="a">DE-92</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/2</subfield><subfield code="2">22</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 150</subfield><subfield code="0">(DE-625)143594:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Lilja, David J.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Designing digital computing systems with Verilog</subfield><subfield code="c">David J. Lilja and Sachin S. Sapatnekar</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Cambridge</subfield><subfield code="b">Cambridge University Press</subfield><subfield code="c">2005</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (ix, 160 pages)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Title from publisher's bibliographic system (viewed on 05 Oct 2015)</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioural and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Verilog (Computer hardware description language)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic digital computers / Design and construction</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Sapatnekar, Sachin S.</subfield><subfield code="d">1967-</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druckausgabe</subfield><subfield code="z">978-0-521-04572-8</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druckausgabe</subfield><subfield code="z">978-0-521-82866-6</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1017/CBO9780511607059</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-20-CBO</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-029352282</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1017/CBO9780511607059</subfield><subfield code="l">DE-12</subfield><subfield code="p">ZDB-20-CBO</subfield><subfield code="q">BSB_PDA_CBO</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1017/CBO9780511607059</subfield><subfield code="l">DE-92</subfield><subfield code="p">ZDB-20-CBO</subfield><subfield code="q">FHN_PDA_CBO</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV043943312 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T17:49:20Z |
| institution | BVB |
| isbn | 9780511607059 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-029352282 |
| oclc_num | 850830959 |
| open_access_boolean | |
| owner | DE-12 DE-92 |
| owner_facet | DE-12 DE-92 |
| physical | 1 online resource (ix, 160 pages) |
| psigel | ZDB-20-CBO ZDB-20-CBO BSB_PDA_CBO ZDB-20-CBO FHN_PDA_CBO |
| publishDate | 2005 |
| publishDateSearch | 2005 |
| publishDateSort | 2005 |
| publisher | Cambridge University Press |
| record_format | marc |
| spelling | Lilja, David J. Verfasser aut Designing digital computing systems with Verilog David J. Lilja and Sachin S. Sapatnekar Cambridge Cambridge University Press 2005 1 online resource (ix, 160 pages) txt rdacontent c rdamedia cr rdacarrier Title from publisher's bibliographic system (viewed on 05 Oct 2015) This book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioural and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers Verilog (Computer hardware description language) Electronic digital computers / Design and construction VERILOG (DE-588)4268385-3 gnd rswk-swf VERILOG (DE-588)4268385-3 s DE-604 Sapatnekar, Sachin S. 1967- Sonstige oth Erscheint auch als Druckausgabe 978-0-521-04572-8 Erscheint auch als Druckausgabe 978-0-521-82866-6 https://doi.org/10.1017/CBO9780511607059 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Lilja, David J. Designing digital computing systems with Verilog Verilog (Computer hardware description language) Electronic digital computers / Design and construction VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4268385-3 |
| title | Designing digital computing systems with Verilog |
| title_auth | Designing digital computing systems with Verilog |
| title_exact_search | Designing digital computing systems with Verilog |
| title_full | Designing digital computing systems with Verilog David J. Lilja and Sachin S. Sapatnekar |
| title_fullStr | Designing digital computing systems with Verilog David J. Lilja and Sachin S. Sapatnekar |
| title_full_unstemmed | Designing digital computing systems with Verilog David J. Lilja and Sachin S. Sapatnekar |
| title_short | Designing digital computing systems with Verilog |
| title_sort | designing digital computing systems with verilog |
| topic | Verilog (Computer hardware description language) Electronic digital computers / Design and construction VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Verilog (Computer hardware description language) Electronic digital computers / Design and construction VERILOG |
| url | https://doi.org/10.1017/CBO9780511607059 |
| work_keys_str_mv | AT liljadavidj designingdigitalcomputingsystemswithverilog AT sapatnekarsachins designingdigitalcomputingsystemswithverilog |