Verfügbarkeit: Abstractions for performance programming on multi-core architectures with hierarchical memory

Abstractions for performance programming on multi-core architectures with hierarchical memory:

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Bibliographische Detailangaben
Beteilige Person:	Terboven, Christian (VerfasserIn)
Format:	Hochschulschrift/Dissertation Buch
Sprache:	Englisch
Veröffentlicht:	Aachen Apprimus Verlag 2016
Ausgabe:	1. Auflage
Schriftenreihe:	Ergebnisse aus der Informatik 7 Edition Wissenschaft Apprimus
Schlagwörter:	NUMA-Architektur OpenMP Parallelverarbeitung Programmierung Speicherhierarchie Mehrkernprozessor Abstraktionsebene Gemeinsamer Speicher Mehrprozessorsystem Hochschulschrift
Links:	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=029153207&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
Umfang:	II, 160 Seiten Diagramme
ISBN:	9783863594428

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Datensatz im Suchindex

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adam_text	CONTENTS 1. INTRODUCTION 1 1.1. MOTIVATION AND G O A LS ............................................................................. 4 1.2. C ONTRIBUTIONS........................................................................................... 7 1.3. THESIS S TRU C TU R E ..................................................................................... 9 2. BENCHMARKS AND SYSTEM ARCHITECTURES 11 2.1. NUMA SYSTEM ARCHITECTURES ............................................................... 12 2.1.1. 2-SOCKET INTEL WESTMERE-EP S Y S TE M ........................................ 13 2.1.2. BULL BGS SYSTEM (INTEL NEHALEM-EX) ..................................... 13 2.2. LINUX PAGE S IZ E S ..................................................................................... 15 2.3. SPECIFIC K ERNELS........................................................................................ 16 2.3.1. STR E A M ..................................................................................... 18 2.3.2. SPARSE-MATRIX-VECTOR-MULTIPLICATION (SPMXV) ......................... 22 2.3.3. GENERALIZED MINIMAL RESIDUAL METHOD (G M RES) ................. 26 2.4. BENCHMARK M ETHODOLOGY...........................................................................27 3. SOFTWARE DESIGN FOR NUMA ARCHITECTURES 31 3.1. PERFORMANCE MODELING AND MACHINE C HARACTERISTICS ............................. 32 3.1.1. PERFORMANCE MODELING OF THE SPMXV K ERNEL..........................36 3.1.2. PERFORMANCE MODELING RESULTS OF STREAM ............................ 43 3.2. RELATED W O RK ...............................................................................................44 3.2.1. EXPLOITATION OF AND OPTIMIZATION FOR NUM A..........................44 3.2.2. THREAD BINDING ON NUMA ..........................................................45 3.2.3. EXTENDING PROGRAMMING MODELS TOWARDS N U M A ..................... 45 3.3. QUANTIFYING THREAD A FFIN ITY .....................................................................46 3.3.1. MACHINE MODEL: DISTANCE M ATRIX ................................................. 47 3.3.2. DISTANCE MATRICES FOR BENCHMARK A RCHITECTURES ....................... 49 3.4. THREAD AFFINITY STRATEGIES ........................................................................51 3.4.1. THREAD AFFINITY REQUIREMENTS.......................................................55 3.4.2. THREAD AFFINITY MODEL: P L A C E S ....................................................58 3.4.3. THREAD AFFINITY MODEL: POLICIES....................................................60 3.4.4. FINAL MEASUREMENTS WITH THE THREAD AFFINITY M O D E L ........... 64 3.5. MEMORY A FFIN ITY .........................................................................................66 3.5.1. SUPPORT FOR NESTED P ARALLELISM ....................................................70 3.5.2. TASKS ON NUMA: PROGRAMMING P A TTE R N S ............................... 71 CONTENTS 3.5.3. TASKS ON NUMA: IMPLEMENTATION COMPARISON...........................77 3.5.4. TOWARDS EXPLICIT MEMORY AFFINITY IN O P EN M P ....................... 79 3.5.5. TOWARDS IMPROVED OS SUPPORT FOR N U M A ............................ 85 3.6. RESULTS AND D ISCUSSION............................................................................ 88 4. PARALLELIZATION WITH OBJECT-ORIENTED ABSTRACTIONS 91 4.1. STATE OF THE ART AND RELATED W O RK ...................................................... 92 4.2. THREAD- AND TASK-BASED ABSTRACTIONS FOR P ARALLELISM ....................... 94 4.2.1. CLASS DESIGN FOR SPARSE LINEAR ALGEBRA K E RN E LS .................... 100 4.2.2. PARALLEL IMPLEMENTATION: STRATEGY P A TTE R N .............................. 104 4.2.3. IMPLEMENTATION AS A LIBRARY: TEMPLATE M ETHOD ....................... 107 4.2.4. EMPLOYMENT IN EXISTING CODES: ADAPTER P A TTE R N ................... 108 4.3. ABSTRACTIONS FOR NUM A............................................................................109 4.3.1. MEMORY MANAGEMENT: ALLOCATOR P A TTE R N ................................. 109 4.3.2. ARCHITECTURE EXAMINATION: SINGLETON PATTERN .........................112 4.4. SUPPORT FOR CLASS-TYPE VARIABLES IN O P EN M P .......................................114 4.4.1. SCOPING S EM A N TIC......................................................................... 114 4.4.2. THREAD SAFETY OF STL D A TA TY P E S .................................................117 4.5. RESULTS AND D ISCUSSION............................................................................118 5. APPLICATION CASE STUDIES 121 5.1. JACOBI M E TH O D .......................................................................................... 121 5.2. FLEXIBLE IMAGE RETRIEVAL ENGINE (F IR E ) ................................................. 123 5.3. NAVIER-STOKES SOLVER DROPS (D R O P S ) ............................................... 125 5.4. SHORT APPLICATION CASE S TU D IE S ..............................................................126 5.4.1. V RFEM .......................................................................................... 127 5.4.2. MULTI-THREADING IN N E S T ...........................................................127 6. SUMMARY AND OUTLOOK 133 LIST OF FIGURES 137 LIST OF TABLES 140 STATEMENT OF ORIGINALITY 151 A. APPENDIX 155 A.L. RELATED SOURCE C ODE..................................................................................155 A. 1.1. HEAPMANAGER ............................................................................. 155 A. 1.2. DISTRIBUTEDOM PALLOCATOR ......................................................... 156 A. 1.3. SCOPETIMER................................................................................... 158 A.2. ACRONYMS AND NOMENCLATURE ................................................................... 160
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spellingShingle	Terboven, Christian Abstractions for performance programming on multi-core architectures with hierarchical memory NUMA-Architektur (DE-588)1123829519 gnd OpenMP (DE-588)4648816-9 gnd Parallelverarbeitung (DE-588)4075860-6 gnd Programmierung (DE-588)4076370-5 gnd Speicherhierarchie (DE-588)4256353-7 gnd Mehrkernprozessor (DE-588)7598578-0 gnd Abstraktionsebene (DE-588)4254804-4 gnd Gemeinsamer Speicher (DE-588)4294156-8 gnd Mehrprozessorsystem (DE-588)4038397-0 gnd
subject_GND	(DE-588)1123829519 (DE-588)4648816-9 (DE-588)4075860-6 (DE-588)4076370-5 (DE-588)4256353-7 (DE-588)7598578-0 (DE-588)4254804-4 (DE-588)4294156-8 (DE-588)4038397-0 (DE-588)4113937-9
title	Abstractions for performance programming on multi-core architectures with hierarchical memory
title_auth	Abstractions for performance programming on multi-core architectures with hierarchical memory
title_exact_search	Abstractions for performance programming on multi-core architectures with hierarchical memory
title_full	Abstractions for performance programming on multi-core architectures with hierarchical memory
title_fullStr	Abstractions for performance programming on multi-core architectures with hierarchical memory
title_full_unstemmed	Abstractions for performance programming on multi-core architectures with hierarchical memory
title_short	Abstractions for performance programming on multi-core architectures with hierarchical memory
title_sort	abstractions for performance programming on multi core architectures with hierarchical memory
topic	NUMA-Architektur (DE-588)1123829519 gnd OpenMP (DE-588)4648816-9 gnd Parallelverarbeitung (DE-588)4075860-6 gnd Programmierung (DE-588)4076370-5 gnd Speicherhierarchie (DE-588)4256353-7 gnd Mehrkernprozessor (DE-588)7598578-0 gnd Abstraktionsebene (DE-588)4254804-4 gnd Gemeinsamer Speicher (DE-588)4294156-8 gnd Mehrprozessorsystem (DE-588)4038397-0 gnd
topic_facet	NUMA-Architektur OpenMP Parallelverarbeitung Programmierung Speicherhierarchie Mehrkernprozessor Abstraktionsebene Gemeinsamer Speicher Mehrprozessorsystem Hochschulschrift
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=029153207&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT terbovenchristian abstractionsforperformanceprogrammingonmulticorearchitectureswithhierarchicalmemory AT apprimusverlag abstractionsforperformanceprogrammingonmulticorearchitectureswithhierarchicalmemory

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