Verfügbarkeit: Device aging in analog circuits for nanoelectronic CMOS technologies

Device aging in analog circuits for nanoelectronic CMOS technologies:

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Bibliographische Detailangaben
Beteilige Person:	Chouard, Florian Raoul (VerfasserIn)
Format:	Hochschulschrift/Dissertation Buch
Sprache:	Englisch
Veröffentlicht:	2012
Schlagwörter:	Hochschulschrift
Links:	http://mediatum.ub.tum.de/node?id=1095220 https://nbn-resolving.org/urn:nbn:de:bvb:91-diss-20120709-1095220-1-4 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=025184368&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
Umfang:	VI, 157 Bl. Ill., graph. Darst.

Internformat

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Datensatz im Suchindex

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adam_text	IMAGE 1 C O N T E N T S 1 S U M M A R Y I 2 I N T R O D U C T I O N 1 2.1 MOTIVATION 1 2.2 STATE-OF-THE-ART IN CIRCUIT RELIABILITY RESEARCH 2 2.3 CONTRIBUTIONS OF THIS WORK 4 3 A G I N G P H Y S I C S 6 3.1 CMOS DEVICE WEAROUT 6 3.2 IMPACT ON DEVICE PARAMETERS 6 3.3 BIAS TEMPERATURE INSTABILITY (BTI) 8 3.3.1 NBTI IN PMOSFETS 9 3.3.2 PBTI IN NMOSFETS 11 3.3.3 PBTI/PMOS AND NBTI/NMOS 13 3.4 HOT-CARRIER INJECTION (HCI) 14 3.4.1 CONDUCTIVE HOT-CARRIER INJECTION IN NMOSFETS 15 3.4.2 CONDUCTIVE HOT-CARRIER INJECTION IN PMOSFETS 17 3.4.3 NON-CONDUCTIVE HOT-CARRIER INJECTION IN NMOSFETS AND PMOSFETS 18 3.5 AGING EFFECT MODELING 18 3.5.1 SEMI-EMPIRICAL MODELS 20 3.5.2 COMPLEX MODELS 22 3.5.3 RELAXATION MODEL 23 3.6 CIRCUIT RELIABILITY SIMULATION 25 3.7 RELIABILITY TESTING 26 3.8 END-OF-LIFETIME USE CASES 27 3.9 TREND 28 III HTTP://D-NB.INFO/1026301483 IMAGE 2 C O N T E N T S IV 3.10 SUMMARY 31 4 D E V I C E A G I N G I N CIRCUIT O P E R A T I O N 3 2 4.1 DIGITAL AND ANALOG CIRCUIT OPERATION 32 4.1.1 CIRCUIT DESIGN PROPERTIES 33 4.1.2 OPERATION CONDITIONS 34 4.1.3 IMPACT ON DEVICE CHARACTERISTIC 38 4.1.4 GENERAL IMPACT ON CIRCUIT CHARACTERISTIC 43 4.1.5 MOS VARACTOR AGING BEHAVIOR MODEL: A CASE STUDY 43 4.2 ADVANCED ANALOG RELATED AGING TESTS 46 4.2.1 OPEN ANALOG RELATED DEVICE AGING TOPICS 46 4.2.2 CUSTOM TEST CIRCUIT 47 4.2.3 STRESS TEST APPROACH 48 4.2.4 STRESS TEST EVALUATION 51 4.2.5 ADVANCED STRESS TEST EVALUATION 59 4.3 SUMMARY 64 5 CURRENT MIRRORS A N D R E F E R E N C E CIRCUITS 6 6 5.1 BASICS 66 5.2 CURRENT MIRROR FUNDAMENTALS 66 5.2.1 CIRCUIT TOPOLOGY . * 66 5.2.2 DESIGN FUNDAMENTALS 67 5.2.3 OPERATION CONDITIONS 68 5.3 CURRENT MIRROR AGING MODEL 68 5.3.1 ANALYTICAL MISMATCH DERIVATION 68 5.3.2 MODEL EVALUATION 70 5.4 REFERENCE CIRCUIT CASE STUDY: SELF-BIASING CURRENT REFERENCE 75 5.4.1 CIRCUIT FUNDAMENTALS 75 5.4.2 AGING BEHAVIOR 76 5.4.3 TRANSFER TO GENERAL REFERENCE CIRCUITS 77 5.5 SUMMARY 77 6 AMPLIFIERS 7 9 6.1 CIRCUIT FUNDAMENTALS 79 IMAGE 3 CONTENTS V 6.1.1 AMPLIFIER BASICS 79 6.1.2 CIRCUIT TOPOLOGIES 80 6.1.3 DESIGN FUNDAMENTALS 82 6.1.4 OPERATION CONDITIONS . . 82 6.1.5 CIRCUIT AGING AND AFFECTED PERFORMANCE PARAMETERS 83 6.1.6 AGING COUNTERMEASURES 85 6.1.7 STATE-OF-THE-ART DIFFERENTIAL MILLER AMPLIFIER 87 6.2 AMPLIFIER AGING MODEL 89 6.2.1 ANALYTIC MODEL DERIVATION 90 6.2.2 MODEL EVALUATION: TWO STAGE MILLER COMPENSATED AMPLIFIER . . . . 92 6.3 STRESS TESTBENCH 96 6.4 ADVANCED CIRCUIT LEVEL AGING APPROACHES 98 6.4.1 ACCELERATED CIRCUIT LEVEL AGING FOR TEST 98 6.4.2 EFFECT RECOVERY MEASUREMENTS 102 6.4.3 AGING SUPPRESSION AND CALIBRATION APPROACH 106 6.5 SUMMARY 112 7 LC-OSCILLATORS 115 7.1 CIRCUIT FUNDAMENTALS 115 7.1.1 VCO PERFORMANCE CHARACTERISTICS 117 7.1.2 DESIGN FUNDAMENTALS * 118 7.1.3 EXEMPLARY CIRCUIT TOPOLOGIES AND DESIGN FLOW 119 7.1.4 CIRCUIT OPERATION INDUCED DEVICE AGING 119 7.1.5 CIRCUIT AGING AND AFFECTED PARAMETERS 120 7.1.6 STATE-OF-THE-ART LC-VCO 122 7.2 LC-VOLTAGE CONTROLLED OSCILLATOR AGING MODEL 125 7.2.1 ANALYTIC MODEL DERIVATION 125 7.2.2 MODEL EVALUATION 126 7.3 STRESS TESTBENCH 127 7.4 ACCELERATED CIRCUIT LEVEL AGING FOR TEST 128 7.4.1 AGING ACCELERATION FOR LC-VCOS 128 7.4.2 AGING USE CASE AND DERIVATION OF STRESS CONDITIONS 129 7.4.3 STRESS TEST SEQUENCE 130 7.4.4 CONCEPT EVALUATION 131 IMAGE 4 CONTENTS 7.4.5 MODEL PREDICTION TO FUTURE LC-VCO IMPLEMENTATIONS 133 7.5 SUMMARY 134 8 C O N C L U S I O N 1 3 6 P U B L I C A T I O N S B Y T H E A U T H O R 1 5 0 A B B R E V I A T I O N S 1 5 2 S Y M B O L S 1 5 4 A C K N O W L E D G M E N T 1 5 7
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spellingShingle	Chouard, Florian Raoul Device aging in analog circuits for nanoelectronic CMOS technologies
subject_GND	(DE-588)4113937-9
title	Device aging in analog circuits for nanoelectronic CMOS technologies
title_auth	Device aging in analog circuits for nanoelectronic CMOS technologies
title_exact_search	Device aging in analog circuits for nanoelectronic CMOS technologies
title_full	Device aging in analog circuits for nanoelectronic CMOS technologies Florian Raoul Chouard
title_fullStr	Device aging in analog circuits for nanoelectronic CMOS technologies Florian Raoul Chouard
title_full_unstemmed	Device aging in analog circuits for nanoelectronic CMOS technologies Florian Raoul Chouard
title_short	Device aging in analog circuits for nanoelectronic CMOS technologies
title_sort	device aging in analog circuits for nanoelectronic cmos technologies
topic_facet	Hochschulschrift
url	http://mediatum.ub.tum.de/node?id=1095220 https://nbn-resolving.org/urn:nbn:de:bvb:91-diss-20120709-1095220-1-4 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=025184368&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT chouardflorianraoul deviceaginginanalogcircuitsfornanoelectroniccmostechnologies

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