Verfügbarkeit: Robust design of DRAM core circuits | Technische Universität München

Robust design of DRAM core circuits: yield estimation and analysis by a statistical design approach

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Bibliographische Detailangaben
Beteilige Person:	Li, Yan 1977- (VerfasserIn)
Format:	Hochschulschrift/Dissertation Elektronisch E-Book
Sprache:	Englisch
Veröffentlicht:	2010
Schlagwörter:	Leseverstärker Leckstrom Schaltungsentwurf Dynamisches RAM Speicherzelle Schaltungsanalyse CMOS Chip Hochschulschrift
Links:	http://mediatum2.ub.tum.de/node?id=992644 http://d-nb.info/1005833079/34 https://nbn-resolving.org/urn:nbn:de:bvb:91-diss-20100129-992644-1-3
Umfang:	1 Online-Ressource

Internformat

MARC


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Datensatz im Suchindex

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spelling	Li, Yan 1977- Verfasser (DE-588)142077437 aut Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach Yan Li 2010 1 Online-Ressource txt rdacontent c rdamedia cr rdacarrier München, Techn. Univ., Diss., 2010 Leseverstärker (DE-588)4716189-9 gnd rswk-swf Leckstrom (DE-588)4382059-1 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Dynamisches RAM (DE-588)4150935-3 gnd rswk-swf Speicherzelle (DE-588)4182147-6 gnd rswk-swf Schaltungsanalyse (DE-588)4179387-0 gnd rswk-swf CMOS (DE-588)4010319-5 gnd rswk-swf Chip (DE-588)4197163-2 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Dynamisches RAM (DE-588)4150935-3 s Leseverstärker (DE-588)4716189-9 s CMOS (DE-588)4010319-5 s Speicherzelle (DE-588)4182147-6 s Chip (DE-588)4197163-2 s Schaltungsentwurf (DE-588)4179389-4 s Schaltungsanalyse (DE-588)4179387-0 s Leckstrom (DE-588)4382059-1 s DE-604 PDF http://mediatum2.ub.tum.de/node?id=992644 Verlag kostenfrei Volltext http://d-nb.info/1005833079/34 Langzeitarchivierung Nationalbibliothek Volltext https://nbn-resolving.org/urn:nbn:de:bvb:91-diss-20100129-992644-1-3 Resolving-System Volltext
spellingShingle	Li, Yan 1977- Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach Leseverstärker (DE-588)4716189-9 gnd Leckstrom (DE-588)4382059-1 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Dynamisches RAM (DE-588)4150935-3 gnd Speicherzelle (DE-588)4182147-6 gnd Schaltungsanalyse (DE-588)4179387-0 gnd CMOS (DE-588)4010319-5 gnd Chip (DE-588)4197163-2 gnd
subject_GND	(DE-588)4716189-9 (DE-588)4382059-1 (DE-588)4179389-4 (DE-588)4150935-3 (DE-588)4182147-6 (DE-588)4179387-0 (DE-588)4010319-5 (DE-588)4197163-2 (DE-588)4113937-9
title	Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach
title_auth	Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach
title_exact_search	Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach
title_full	Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach Yan Li
title_fullStr	Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach Yan Li
title_full_unstemmed	Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach Yan Li
title_short	Robust design of DRAM core circuits
title_sort	robust design of dram core circuits yield estimation and analysis by a statistical design approach
title_sub	yield estimation and analysis by a statistical design approach
topic	Leseverstärker (DE-588)4716189-9 gnd Leckstrom (DE-588)4382059-1 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Dynamisches RAM (DE-588)4150935-3 gnd Speicherzelle (DE-588)4182147-6 gnd Schaltungsanalyse (DE-588)4179387-0 gnd CMOS (DE-588)4010319-5 gnd Chip (DE-588)4197163-2 gnd
topic_facet	Leseverstärker Leckstrom Schaltungsentwurf Dynamisches RAM Speicherzelle Schaltungsanalyse CMOS Chip Hochschulschrift
url	http://mediatum2.ub.tum.de/node?id=992644 http://d-nb.info/1005833079/34 https://nbn-resolving.org/urn:nbn:de:bvb:91-diss-20100129-992644-1-3
work_keys_str_mv	AT liyan robustdesignofdramcorecircuitsyieldestimationandanalysisbyastatisticaldesignapproach

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