Techniques for increasing security and reliability of IP cores embedded in FPGA and ASIC designs:
Gespeichert in:
| Beteilige Person: | |
|---|---|
| Format: | Hochschulschrift/Dissertation Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
München
Hut
2010
|
| Schlagwörter: | |
| Links: | https://open.fau.de/handle/openfau/9273 https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-92738 http://d-nb.info/1150968001/34 |
| Umfang: | VIII, 317 S. 240 mm x 170 mm |
| ISBN: | 9783868536577 |
Internformat
MARC
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| 245 | 1 | 0 | |a Techniques for increasing security and reliability of IP cores embedded in FPGA and ASIC designs |c Daniel Ziener |
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Datensatz im Suchindex
| DE-BY-TUM_call_number | 0001 2011 A 886 |
|---|---|
| DE-BY-TUM_katkey | 1755018 |
| DE-BY-TUM_location | Mag |
| DE-BY-TUM_media_number | 040007312601 |
| _version_ | 1821933314295988224 |
| any_adam_object | |
| author | Ziener, Daniel |
| author_GND | (DE-588)142977179 |
| author_facet | Ziener, Daniel |
| author_role | aut |
| author_sort | Ziener, Daniel |
| author_variant | d z dz |
| building | Verbundindex |
| bvnumber | BV036850231 |
| classification_rvk | ST 153 ST 233 ST 277 |
| collection | ebook |
| ctrlnum | (OCoLC)706029102 (DE-599)DNB1008314536 |
| discipline | Informatik |
| format | Thesis Book |
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| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV036850231 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T14:43:13Z |
| institution | BVB |
| isbn | 9783868536577 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-020766210 |
| oclc_num | 706029102 |
| open_access_boolean | 1 |
| owner | DE-29 DE-12 DE-91 DE-BY-TUM DE-29T |
| owner_facet | DE-29 DE-12 DE-91 DE-BY-TUM DE-29T |
| physical | VIII, 317 S. 240 mm x 170 mm |
| psigel | ebook |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Hut |
| record_format | marc |
| spellingShingle | Ziener, Daniel Techniques for increasing security and reliability of IP cores embedded in FPGA and ASIC designs |
| subject_GND | (DE-588)4113937-9 |
| title | Techniques for increasing security and reliability of IP cores embedded in FPGA and ASIC designs |
| title_auth | Techniques for increasing security and reliability of IP cores embedded in FPGA and ASIC designs |
| title_exact_search | Techniques for increasing security and reliability of IP cores embedded in FPGA and ASIC designs |
| title_full | Techniques for increasing security and reliability of IP cores embedded in FPGA and ASIC designs Daniel Ziener |
| title_fullStr | Techniques for increasing security and reliability of IP cores embedded in FPGA and ASIC designs Daniel Ziener |
| title_full_unstemmed | Techniques for increasing security and reliability of IP cores embedded in FPGA and ASIC designs Daniel Ziener |
| title_short | Techniques for increasing security and reliability of IP cores embedded in FPGA and ASIC designs |
| title_sort | techniques for increasing security and reliability of ip cores embedded in fpga and asic designs |
| topic_facet | Hochschulschrift |
| url | https://open.fau.de/handle/openfau/9273 https://nbn-resolving.org/urn:nbn:de:bvb:29-opus4-92738 http://d-nb.info/1150968001/34 |
| work_keys_str_mv | AT zienerdaniel techniquesforincreasingsecurityandreliabilityofipcoresembeddedinfpgaandasicdesigns |
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Bibliotheksmagazin
| Signatur: |
0001 2011 A 886 Lageplan |
|---|---|
| Exemplar 1 | Ausleihbar Am Standort |