Verfügbarkeit: Robust design of DRAM core circuits | Technische Universität München

Robust design of DRAM core circuits: yield estimation and analysis by a statistical design approach

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Bibliographische Detailangaben
Beteilige Person:	Li, Yan 1977- (VerfasserIn)
Format:	Hochschulschrift/Dissertation Buch
Sprache:	Englisch
Veröffentlicht:	2010
Schlagwörter:	Schaltungsanalyse Leseverstärker Chip CMOS Dynamisches RAM Schaltungsentwurf Speicherzelle Leckstrom Hochschulschrift
Links:	https://mediatum.ub.tum.de/node?id=992644 https://nbn-resolving.org/urn:nbn:de:bvb:91-diss-20100129-992644-1-3
Umfang:	IX, 127 S. graph. Darst.

Internformat

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Datensatz im Suchindex

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spellingShingle	Li, Yan 1977- Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach Schaltungsanalyse (DE-588)4179387-0 gnd Leseverstärker (DE-588)4716189-9 gnd Chip (DE-588)4197163-2 gnd CMOS (DE-588)4010319-5 gnd Dynamisches RAM (DE-588)4150935-3 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Speicherzelle (DE-588)4182147-6 gnd Leckstrom (DE-588)4382059-1 gnd
subject_GND	(DE-588)4179387-0 (DE-588)4716189-9 (DE-588)4197163-2 (DE-588)4010319-5 (DE-588)4150935-3 (DE-588)4179389-4 (DE-588)4182147-6 (DE-588)4382059-1 (DE-588)4113937-9
title	Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach
title_auth	Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach
title_exact_search	Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach
title_full	Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach Yan Li
title_fullStr	Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach Yan Li
title_full_unstemmed	Robust design of DRAM core circuits yield estimation and analysis by a statistical design approach Yan Li
title_short	Robust design of DRAM core circuits
title_sort	robust design of dram core circuits yield estimation and analysis by a statistical design approach
title_sub	yield estimation and analysis by a statistical design approach
topic	Schaltungsanalyse (DE-588)4179387-0 gnd Leseverstärker (DE-588)4716189-9 gnd Chip (DE-588)4197163-2 gnd CMOS (DE-588)4010319-5 gnd Dynamisches RAM (DE-588)4150935-3 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Speicherzelle (DE-588)4182147-6 gnd Leckstrom (DE-588)4382059-1 gnd
topic_facet	Schaltungsanalyse Leseverstärker Chip CMOS Dynamisches RAM Schaltungsentwurf Speicherzelle Leckstrom Hochschulschrift
url	https://mediatum.ub.tum.de/node?id=992644 https://nbn-resolving.org/urn:nbn:de:bvb:91-diss-20100129-992644-1-3
work_keys_str_mv	AT liyan robustdesignofdramcorecircuitsyieldestimationandanalysisbyastatisticaldesignapproach

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