Analog circuits and systems optimization based on evolutionary computation techniques:
Gespeichert in:
| Beteiligte Personen: | , , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Berlin [u.a.]
Springer
2010
|
| Schriftenreihe: | Studies in computational intelligence
294 |
| Schlagwörter: | |
| Links: | http://deposit.dnb.de/cgi-bin/dokserv?id=3435210&prov=M&dok_var=1&dok_ext=htm http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=020408113&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| Umfang: | XXIV, 230 S. graph. Darst. |
| ISBN: | 9783642123450 |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV036485409 | ||
| 003 | DE-604 | ||
| 005 | 20100714 | ||
| 007 | t| | ||
| 008 | 100604s2010 xx d||| |||| 00||| eng d | ||
| 016 | 7 | |a 1000569039 |2 DE-101 | |
| 020 | |a 9783642123450 |9 978-3-642-12345-0 | ||
| 020 | |z 9783642123467 |c eISBN |9 978-3-642-12346-7 | ||
| 035 | |a (OCoLC)631692298 | ||
| 035 | |a (DE-599)DNB1000569039 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-11 |a DE-83 |a DE-634 | ||
| 082 | 0 | |a 621.38150285 |2 22/ger | |
| 084 | |a ST 300 |0 (DE-625)143650: |2 rvk | ||
| 084 | |a ZN 4904 |0 (DE-625)157419: |2 rvk | ||
| 084 | |a 004 |2 sdnb | ||
| 084 | |a 620 |2 sdnb | ||
| 100 | 1 | |a Barros, Manuel F. M. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Analog circuits and systems optimization based on evolutionary computation techniques |c Manuel F. M. Barros ; Jorge M. C. Guilherme ; Nuno C. G. Horta |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 2010 | |
| 300 | |a XXIV, 230 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Studies in computational intelligence |v 294 | |
| 650 | 0 | 7 | |a Analogschaltung |0 (DE-588)4122796-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Evolutionärer Algorithmus |0 (DE-588)4366912-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Analogschaltung |0 (DE-588)4122796-7 |D s |
| 689 | 0 | 1 | |a Entwurfsautomation |0 (DE-588)4312536-0 |D s |
| 689 | 0 | 2 | |a Evolutionärer Algorithmus |0 (DE-588)4366912-8 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Guilherme, Jorge M. C. |e Verfasser |4 aut | |
| 700 | 1 | |a Horta, Nuno C. G. |e Verfasser |4 aut | |
| 830 | 0 | |a Studies in computational intelligence |v 294 |w (DE-604)BV020822171 |9 294 | |
| 856 | 4 | 2 | |q text/html |u http://deposit.dnb.de/cgi-bin/dokserv?id=3435210&prov=M&dok_var=1&dok_ext=htm |3 Inhaltstext |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=020408113&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-020408113 | |
Datensatz im Suchindex
| _version_ | 1819301871920087040 |
|---|---|
| adam_text | REFERENCES 44 CONTENTS 1 INTRODUCTION 1 1.1 MICROELECTRONICS MARKET AND
TECHNOLOGY EVOLUTION 1 1.2 ANALOG INTEGRATED CIRCUIT DESIGN 3 1.2.1
ANALOG DESIGN ISSUES 3 1.2.2 THE HIERARCHICAL DECOMPOSITION MODEL 4
1.2.3 ANALOG IC DESIGN FLOW 5 1.2.4 ANALOG DESIGN FLOW OF A 15-BIT
PIPELINE CMOS A/D CONVERTER 8 1.3 ANALOG DESIGN AUTOMATION 10 1.3.1 CAD
TOOLS FOR ANALOG CIRCUIT DESIGN 10 1.3.2 AUTOMATED ANALOG IC DESIGN 11
REFERENCES 14 2 STATE-OF-THE-ART ON ANALOG DESIGN AUTOMATION 19 2.1
TRENDS IN DESIGN AUTOMATION METHODOLOGY 19 2.1.1 AUTOMATED TOPOLOGY
SELECTION 20 2.1.2 AUTOMATED CIRCUIT SIZING/OPTIMIZATION 23 2.1.3
AUTOMATED LAYOUT GENERATION 23 2.2 AUTOMATED CIRCUIT SYNTHESIS
APPROACHES 26 2.2.1 KNOWLEDGE-BASED APPROACH 26 2.2.2 OPTIMIZATION-BASED
APPROACH 27 2.2.2.1 EQUATION-BASED METHODS 28 2.2.2.2 SIMULATION-BASED
METHODS 29 2.2.2.3 LEARNING-BASED METHODS 30 2.2.3 COMMERCIAL TOOLS 31
2.3 DESIGN AUTOMATION TOOLS: COMPARATIVE ANALYSIS 31 2.3.1 SPECIFIC
CHARACTERISTICS 36 2.3.2 PERFORMANCE ANALYSIS 37 2.3.3 OPTIMIZATION
TECHNIQUES 38 2.3.4 OTHER CHARACTERISTICS 40 2.3.5 SUMMARY 40 2.4 GENOM
OPTIMIZATION TOOL: IMPLEMENTATION GOALS 42 2.5 CONCLUSIONS 43
BIBLIOGRAFISCHE INFORMATIONEN HTTP://D-NB.INFO/1000569039 DIGITALISIERT
DURCH X CONTENTS 3 EVOLUTIONARY ANALOG IC DESIGN OPTIMIZATION 49 3.1
COMPUTATION TECHNIQUES FOR ANALOG IC DESIGN - AN OVERVIEW 49 3.1.1
ANALOG IC DESIGN PROBLEM FORMULATION 49 3.1.2 NUMERIC PROGRAMMING
TECHNIQUES 51 3.1.3 THE NO-FREE-LUNCH THEOREM 52 3.1.4 EVOLUTIONARY
COMPUTATION TECHNIQUES OVERVIEW 54 3.2 KEY ISSUES IN EVOLUTIONARY SEARCH
57 3.3 GENOM - EVOLUTIONARY KERNEL FOR ANALOG IC DESIGN OPTIMIZATION
....61 3.3.1 FITNESS FUNCTION STUDY 61 3.3.1.1 MULTI-OBJECTIVE COST
FUNCTION 62 3.3.1.2 COST FUNCTION WITH NO PREFERENCE ARTICULATION 65
3.3.2 INDIVIDUAL ENCODING, POPULATION STRUCTURE AND SAMPLING 67 3.3.3
SELECTION STRATEGIES 71 3.3.3.1 RANKING-BASED SCHEME 71 3.3.3.2
CONSTRAINT-BASED SELECTION 72 3.3.4 CROSSOVER STRATEGIES 73 3.3.5
MUTATION STRATEGIES 74 3.3.6 STEP SIZE CONTROL - DYNAMIC EVOLUTIONARY
CONTROL 76 3.3.7 A DISTRIBUTED ALGORITHM FOR TIME CONSUMING FITNESS
FUNCTIONS 77 3.3.8 GENOM GA ATTRIBUTES 80 3.3.9 GENOM OPTIMIZATION
METHODOLOGY 82 3.3.9.1 OPTIMIZATION SETUP 82 3.3.9.2 COARSE OPTIMIZATION
83 3.3.9.3 FINE-TUNING OPTIMIZATION 83 3.4 CONCLUSIONS 84 REFERENCES 84
4 ENHANCED TECHNIQUES FOR ANALOG CIRCUITS DESIGN USING SVM MODELS 89 4.1
LEARNING ALGORITHMS OVERVIEW 89 4.1.1 SVM CLASSIFICATION OVERVIEW 95 4.2
GA-SVM OPTIMIZATION APPROACH 96 4.2.1 FEASIBILITY REGION DEFINITION 96
4.2. CONTENTS XI 5 ANALOG IC DESIGN ENVIRONMENT ARCHITECTURE 109 5.1
AIDA ARCHITECTURE 109 5.1.1 AIDA IN-HOUSE DESIGN ENVIRONMENT OVERVIEW
109 5.1.2 LAYOUT LEVEL TOOLS 112 5.2 GENOM SYSTEM OVERVIEW 112 5.2.1
DESIGN FLOW 113 5.2.2 INPUT DATA 114 5.2.3 OUTPUT DATA 120 5.2.3.1
PROGRESS REAL-TIME REPORTS 121 5.2.3.2 INTERACTIVE DESIGN 122 5.2.4 I/O
INTERFACES 123 5.2.5 EVALUATION ENGINE 125 5.2.6 EXPANSION OF GENOM TOOL
125 5.2.7 OPTIMIZATION KERNEL CONFIGURATION 127 5.3 DATA FLOW MANAGEMENT
128 5.3.1 INPUT DATA SPECIFICATION 129 5.3.2 EVALUATION/SIMULATION DATA
HARDWARE 131 5.3.3 OUTPUT DATA 133 5.3.3.1 THE SIMULATION AND EQUATION
BASED COST FUNCTION PARSER 134 5.4 CONCLUSIONS 136 REFERENCES 137 6
OPTIMIZATION OF ANALOG CIRCUITS AND SYSTEMS - APPLICATIONS 139 6.1
TESTING THE PERFORMANCE OF ANALOG CIRCUITS 139 6.2 TESTING THE GENOM -
SELECTED CIRCUIT TOPOLOGIES 141 6.3 GENOM CONVERGENCE TESTS 144 6.3.1
THE ANALOG IC DESIGN APPROACH 145 6.3.2 TESTING THE SELECTION APPROACH
146 6.4 COMPARING GA-STD, GA-MOD AND GA-SVM PERFORMANCE 148 6.4.1 GA-STD
VERSUS GA-SVM PERFORMANCE - FILTER CASE STUDY... 149 6.4.2 STATIC GA-SVM
PERFORMANCE - OPAMP CASE STUDY 151 6.4.2.1 EVALUATION METRIC 153 6.4.3
TESTING THE DYNAMIC GA-SVM PERFORMANCE 154 6.4.4 FINAL COMMENTS 156 6.
XII CONTENTS 6.5.2.4 DESIGN ANALYSIS 170 6.5.3 FOLDED CASCODE OPAMP WITH
AB OUTPUT 172 6.5.3.1 DESCRIPTION 172 6.5.3.2 PROBLEM SPECIFICATIONS AND
DESIGN CONFIGURATIONS .... 173 6.5.3.3 DESIGN ANALYSIS 175 6.6
COMPARISON WITH OTHER TOOLS/APPROACHES 178 6.6.1 FRIDGE BENCHMARK
CIRCUIT TESTS 179 6.6.2 OPTIMIZATION TEST WITH FRIDGE AMPOP 179 6.6.3
COMPARISON RESULTS 182 6.6.4 CORNERS OPTIMIZATION WITH FRIDGE CIRCUIT
183 6.7 CONCLUSIONS 185 REFERENCES 185 7 CONCLUSION 187 7.1 CONCLUSIONS
187 7.2 FUTURE WORK 188 APPENDIXES 191 APPENDIX A. TERMINOLOGY 191
APPENDIX B. GENERAL PURPOSE OPTIMIZATION TECHNIQUES 193 B.I RANDOM
SEARCH METHODS 193 B.2 UNCONSTRAINED GRADIENT-BASED METHODS 193 B.3
CONSTRAINTS PROGRAMMING 194 B.4 DIRECT STOCHASTIC METHODS 195 B.5
MULTIPLE OBJECTIVES 197 APPENDIX C. THE BASIC DECISIONS OF STANDARD GA
ALGORITHMS 199 C.I STANDARD GA KERNEL OPTIMIZATION 199 C.I.I
EVOLUTIONARY KERNEL FRAMEWORK 199 C.1.2 ALGORITHM DESIGN PARAMETERS 200
C.1.3 SINGLE OPTIMIZATION GA EXAMPLE 202 C.2 REPRESENTATION AND ENCODING
205 C.3 FITNESS EVALUATION AND ASSIGNMENT 206 C.4 INITIAL POPULATION 207
C.5 SELECTION 208 C.6 CROSSOVER OPERATOR 209 C.7 MUTATION OPERATOR 211
C.8 PERFORMANCE CRITERIA 212 APPENDIX D. SUPPORT VECTOR MACHINE OVERVIEW
213 D. CONTENTS XIII D.3.2 BOOTSTRAP METHOD 218 D.3.3 CROSS-VALIDATION
METHOD 218 D.4 SVM MODEL EVALUATION 219 D.4.1 KERNEL EVALUATION METRICS
219 D.4.2 MODEL SELECTION PARAMETERS 220 REFERENCES 222 INDEX 227
|
| any_adam_object | 1 |
| author | Barros, Manuel F. M. Guilherme, Jorge M. C. Horta, Nuno C. G. |
| author_facet | Barros, Manuel F. M. Guilherme, Jorge M. C. Horta, Nuno C. G. |
| author_role | aut aut aut |
| author_sort | Barros, Manuel F. M. |
| author_variant | m f m b mfm mfmb j m c g jmc jmcg n c g h ncg ncgh |
| building | Verbundindex |
| bvnumber | BV036485409 |
| classification_rvk | ST 300 ZN 4904 |
| ctrlnum | (OCoLC)631692298 (DE-599)DNB1000569039 |
| dewey-full | 621.38150285 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.38150285 |
| dewey-search | 621.38150285 |
| dewey-sort | 3621.38150285 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Maschinenbau / Maschinenwesen Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02126nam a2200493 cb4500</leader><controlfield tag="001">BV036485409</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20100714 </controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">100604s2010 xx d||| |||| 00||| eng d</controlfield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">1000569039</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9783642123450</subfield><subfield code="9">978-3-642-12345-0</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="z">9783642123467</subfield><subfield code="c">eISBN</subfield><subfield code="9">978-3-642-12346-7</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)631692298</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DNB1000569039</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-11</subfield><subfield code="a">DE-83</subfield><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.38150285</subfield><subfield code="2">22/ger</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 300</subfield><subfield code="0">(DE-625)143650:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4904</subfield><subfield code="0">(DE-625)157419:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">004</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">620</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Barros, Manuel F. M.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Analog circuits and systems optimization based on evolutionary computation techniques</subfield><subfield code="c">Manuel F. M. Barros ; Jorge M. C. Guilherme ; Nuno C. G. Horta</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Berlin [u.a.]</subfield><subfield code="b">Springer</subfield><subfield code="c">2010</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXIV, 230 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Studies in computational intelligence</subfield><subfield code="v">294</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Analogschaltung</subfield><subfield code="0">(DE-588)4122796-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Evolutionärer Algorithmus</subfield><subfield code="0">(DE-588)4366912-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Analogschaltung</subfield><subfield code="0">(DE-588)4122796-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Evolutionärer Algorithmus</subfield><subfield code="0">(DE-588)4366912-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Guilherme, Jorge M. C.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Horta, Nuno C. G.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Studies in computational intelligence</subfield><subfield code="v">294</subfield><subfield code="w">(DE-604)BV020822171</subfield><subfield code="9">294</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="q">text/html</subfield><subfield code="u">http://deposit.dnb.de/cgi-bin/dokserv?id=3435210&prov=M&dok_var=1&dok_ext=htm</subfield><subfield code="3">Inhaltstext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">DNB Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=020408113&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-020408113</subfield></datafield></record></collection> |
| id | DE-604.BV036485409 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T14:35:27Z |
| institution | BVB |
| isbn | 9783642123450 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-020408113 |
| oclc_num | 631692298 |
| open_access_boolean | |
| owner | DE-11 DE-83 DE-634 |
| owner_facet | DE-11 DE-83 DE-634 |
| physical | XXIV, 230 S. graph. Darst. |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Springer |
| record_format | marc |
| series | Studies in computational intelligence |
| series2 | Studies in computational intelligence |
| spellingShingle | Barros, Manuel F. M. Guilherme, Jorge M. C. Horta, Nuno C. G. Analog circuits and systems optimization based on evolutionary computation techniques Studies in computational intelligence Analogschaltung (DE-588)4122796-7 gnd Evolutionärer Algorithmus (DE-588)4366912-8 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| subject_GND | (DE-588)4122796-7 (DE-588)4366912-8 (DE-588)4312536-0 |
| title | Analog circuits and systems optimization based on evolutionary computation techniques |
| title_auth | Analog circuits and systems optimization based on evolutionary computation techniques |
| title_exact_search | Analog circuits and systems optimization based on evolutionary computation techniques |
| title_full | Analog circuits and systems optimization based on evolutionary computation techniques Manuel F. M. Barros ; Jorge M. C. Guilherme ; Nuno C. G. Horta |
| title_fullStr | Analog circuits and systems optimization based on evolutionary computation techniques Manuel F. M. Barros ; Jorge M. C. Guilherme ; Nuno C. G. Horta |
| title_full_unstemmed | Analog circuits and systems optimization based on evolutionary computation techniques Manuel F. M. Barros ; Jorge M. C. Guilherme ; Nuno C. G. Horta |
| title_short | Analog circuits and systems optimization based on evolutionary computation techniques |
| title_sort | analog circuits and systems optimization based on evolutionary computation techniques |
| topic | Analogschaltung (DE-588)4122796-7 gnd Evolutionärer Algorithmus (DE-588)4366912-8 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| topic_facet | Analogschaltung Evolutionärer Algorithmus Entwurfsautomation |
| url | http://deposit.dnb.de/cgi-bin/dokserv?id=3435210&prov=M&dok_var=1&dok_ext=htm http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=020408113&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV020822171 |
| work_keys_str_mv | AT barrosmanuelfm analogcircuitsandsystemsoptimizationbasedonevolutionarycomputationtechniques AT guilhermejorgemc analogcircuitsandsystemsoptimizationbasedonevolutionarycomputationtechniques AT hortanunocg analogcircuitsandsystemsoptimizationbasedonevolutionarycomputationtechniques |