Logic Minimization Algorithms for VLSI synthesis:
Gespeichert in:
| Weitere beteiligte Personen: | |
|---|---|
| Format: | Buch |
| Sprache: | Nichtbestimmte Sprache |
| Veröffentlicht: |
Boston <<[u.a.]>>
Kluwer
1984
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
2 : VLSI computer architecture, and digital signal processing |
| Schlagwörter: | |
| Umfang: | IX, 193 S. |
| ISBN: | 0898381649 |
Internformat
MARC
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Datensatz im Suchindex
| _version_ | 1818968012055642112 |
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| author2 | Brayton, Robert K. |
| author2_role | ctb |
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| author_facet | Brayton, Robert K. |
| building | Verbundindex |
| bvnumber | BV024562628 |
| classification_rvk | ST 190 ZN 4950 |
| ctrlnum | (OCoLC)636742002 (DE-599)BVBBV024562628 |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV024562628 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T13:57:55Z |
| institution | BVB |
| isbn | 0898381649 |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-018536274 |
| oclc_num | 636742002 |
| open_access_boolean | |
| owner | DE-83 |
| owner_facet | DE-83 |
| physical | IX, 193 S. |
| psigel | TUB-nse |
| publishDate | 1984 |
| publishDateSearch | 1984 |
| publishDateSort | 1984 |
| publisher | Kluwer |
| record_format | marc |
| series2 | The Kluwer international series in engineering and computer science |
| spelling | Logic Minimization Algorithms for VLSI synthesis by Robert K. Brayton ... Boston <<[u.a.]>> Kluwer 1984 IX, 193 S. txt rdacontent n rdamedia nc rdacarrier The Kluwer international series in engineering and computer science 2 : VLSI computer architecture, and digital signal processing Synthese (DE-588)4418958-8 gnd rswk-swf Algorithmus (DE-588)4001183-5 gnd rswk-swf Optimierung (DE-588)4043664-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Minimierung (DE-588)4251074-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Synthese (DE-588)4418958-8 s Minimierung (DE-588)4251074-0 s Algorithmus (DE-588)4001183-5 s DE-604 Optimierung (DE-588)4043664-0 s Brayton, Robert K. ctb |
| spellingShingle | Logic Minimization Algorithms for VLSI synthesis Synthese (DE-588)4418958-8 gnd Algorithmus (DE-588)4001183-5 gnd Optimierung (DE-588)4043664-0 gnd VLSI (DE-588)4117388-0 gnd Minimierung (DE-588)4251074-0 gnd |
| subject_GND | (DE-588)4418958-8 (DE-588)4001183-5 (DE-588)4043664-0 (DE-588)4117388-0 (DE-588)4251074-0 |
| title | Logic Minimization Algorithms for VLSI synthesis |
| title_auth | Logic Minimization Algorithms for VLSI synthesis |
| title_exact_search | Logic Minimization Algorithms for VLSI synthesis |
| title_full | Logic Minimization Algorithms for VLSI synthesis by Robert K. Brayton ... |
| title_fullStr | Logic Minimization Algorithms for VLSI synthesis by Robert K. Brayton ... |
| title_full_unstemmed | Logic Minimization Algorithms for VLSI synthesis by Robert K. Brayton ... |
| title_short | Logic Minimization Algorithms for VLSI synthesis |
| title_sort | logic minimization algorithms for vlsi synthesis |
| topic | Synthese (DE-588)4418958-8 gnd Algorithmus (DE-588)4001183-5 gnd Optimierung (DE-588)4043664-0 gnd VLSI (DE-588)4117388-0 gnd Minimierung (DE-588)4251074-0 gnd |
| topic_facet | Synthese Algorithmus Optimierung VLSI Minimierung |
| work_keys_str_mv | AT braytonrobertk logicminimizationalgorithmsforvlsisynthesis |