All-digital frequency synthesizer in deep-submicron CMOS:
Gespeichert in:
| Beteiligte Personen: | , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Hoboken, NJ
Wiley-Interscience
2006
|
| Schlagwörter: | |
| Links: | http://deposit.dnb.de/cgi-bin/dokserv?id=2846002&prov=M&dok_var=1&dok_ext=htm http://www.loc.gov/catdir/toc/fy0705/2006040508.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017443717&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| Umfang: | XVII, 261 S. Ill., graph. Darst. |
| ISBN: | 9780471772552 |
Internformat
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV023801518 | ||
| 003 | DE-604 | ||
| 005 | 20111117 | ||
| 007 | t| | ||
| 008 | 070724s2006 xx ad|| |||| 00||| eng d | ||
| 020 | |a 9780471772552 |9 978-0-471-77255-2 | ||
| 035 | |a (OCoLC)62858087 | ||
| 035 | |a (DE-599)BVBBV023801518 | ||
| 040 | |a DE-604 |b ger | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-634 |a DE-29T | ||
| 082 | 0 | |a 621.3815/486 |2 22 | |
| 100 | 1 | |a Staszewski, Robert Bogdan |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a All-digital frequency synthesizer in deep-submicron CMOS |c Robert Bogdan Staszewski ; Poras T. Balsara |
| 264 | 1 | |a Hoboken, NJ |b Wiley-Interscience |c 2006 | |
| 300 | |a XVII, 261 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Synthesizer |g Elektronik |0 (DE-588)4184253-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CMOS |0 (DE-588)4010319-5 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Synthesizer |g Elektronik |0 (DE-588)4184253-4 |D s |
| 689 | 0 | 1 | |a CMOS |0 (DE-588)4010319-5 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Balsara, Poras T. |e Verfasser |4 aut | |
| 856 | 4 | |u http://deposit.dnb.de/cgi-bin/dokserv?id=2846002&prov=M&dok_var=1&dok_ext=htm |3 Beschreibung für Leser | |
| 856 | 4 | |u http://www.loc.gov/catdir/toc/fy0705/2006040508.html |3 Inhaltsverzeichnis | |
| 856 | 4 | 2 | |m GBV Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017443717&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-017443717 | |
Datensatz im Suchindex
| _version_ | 1819317162115858432 |
|---|---|
| adam_text | ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS ROBERT BOGDAN
STASZEWSKI TEXAS INSTRUMENTS PORAS T. BALSARA UNIVERSITY OF TEXAS AT
DALLAS WILEY- INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION
CONTENTS PREFACE XIII 1 INTRODUCTION 1 1.1 FREQUENCY SYNTHESIS / 1 1.1.1
NOISE IN OSCILLATORS / 2 1.1.2 FREQUENCY SYNTHESIS TECHNIQUES / 5 1.2
FREQUENCY SYNTHESIZER AS AN INTEGRAL PART OF AN RF TRANSCEIVER / 9 1.2.1
TRANSMITTER / 10 1.2.2 RECEIVER / 11 1.2.3 TOWARD DIRECT TRANSMITTER
MODULATION / 12 1.3 FREQUENCY SYNTHESIZERS FOR MOBILE COMMUNICATIONS /
16 1.3.1 INTEGER- N PLL ARCHITECTURE / 17 1.3.2 FRACTIONAL-./V PLL
ARCHITECTURE / 18 1.3.3 TOWARD AN ALL-DIGITAL PLL APPROACH / 23 1.4
IMPLEMENTATION OF AN RF SYNTHESIZER / 25 1.4.1 CMOS VS. TRADITIONAL RF
PROCESS TECHNOLOGIES / 25 1.4.2 DEEP-SUBMICRON CMOS / 25 1.4.3 DIGITALLY
INTENSIVE APPROACH / 26 1.4.4 SYSTEM INTEGRATION / 27 VII VILL CONTENTS
1.4.5 SYSTEM INTEGRATION CHALLENGES FOR DEEP-SUBMICRON CMOS / 29 2
DIGITALLY CONTROLLED OSCILLATOR 2.1 VARACTOR IN A DEEP-SUBMICRON CMOS
PROCESS / 31 2.2 FULLY DIGITAL CONTROL OF OSCILLATING FREQUENCY / 33 2.3
LCTANK / 35 2.4 OSCILLATOR CORE / 37 2.5 OPEN-LOOP NARROWBAND
DIGITAL-TO-FREQUENCY CONVERSION / 39 2.6 EXAMPLE IMPLEMENTATION / 45 2.7
TIME-DOMAIN MATHEMATICAL MODEL OF A DCO / 47 2.8 SUMMARY / 51 3
NORMALIZED DCO 3.1 OSCILLATOR TRANSFER FUNCTION AND GAIN / 52 3.2 DCO
GAIN ESTIMATION / 53 3.3 DCO GAIN NORMALIZATION / 54 3.4 PRINCIPLE OF
SYNCHRONOUSLY OPTIMAL DCO TUNING WORD RETIMING / 55 3.5 TIME DITHERING
OF DCO TUNING INPUT / 56 3.5.1 OSCILLATOR TUNE TIME DITHERING PRINCIPLE
/ 56 3.5.2 DIRECT TIME DITHERING OF TUNING INPUT / 57 3.5.3 UPDATE CLOCK
DITHERING SCHEME / 59 3.6 IMPLEMENTATION OF PVT AND ACQUISITION DCO BITS
/ 60 3.7 IMPLEMENTATION OF TRACKING DCO BITS / 64 3.7.1 HIGH-SPEED
DITHERING OF FRACTIONAL VARACTORS / 64 3.7.2 DYNAMIC ELEMENT MATCHING OF
VARACTORS / 70 3.7.3 DCO VARACTOR REARRANGEMENT / 71 3.8 TIME-DOMAIN
MODEL / 73 3.9 SUMMARY / 74 4 ALL-DIGITAL PHASE-LOCKED LOOP 4.1
PHASE-DOMAIN OPERATION / 77 4.2 REFERENCE CLOCK RETIMING / 79 4.3 PHASE
DETECTION / 81 4.3.1 DIFFERENCE MODE OF ADPLL OPERATION / 85 4.3.2
INTEGER-DOMAIN OPERATION / 86 4.4 MODULO ARITHMETIC OF THE REFERENCE AND
VARIABLE PHASES / 86 4.4.1 VARIABLE-PHASE ACCUMULATOR (PV BLOCK) / 89
CONTENTS IX 4.5 TIME-TO-DIGITAL CONVERTER / 91 4.5.1 FREQUENCY REFERENCE
EDGE ESTIMATION / 93 4.6 FRACTIONAL ERROR ESTIMATOR / 94 4.6.1
FRACTIONAL-DIVISION RATIO COMPENSATION / 96 4.6.2 TDC RESOLUTION EFFECT
ON ESTIMATED FREQUENCY RESOLUTION / 97 4.6.3 ACTIVE REMOVAL OF
FRACTIONAL SPURS THROUGH TDC (OPTIONAL) / 98 4.7 FREQUENCY REFERENCE
RETIMING BY A DCO CLOCK / 100 4.7.1 SENSE AMPLIFIER-BASED FLIP-FLOP /
102 4.7.2 GENERAL IDEA OF CLOCK RETIMING / 103 4.7.3 IMPLEMENTATION /
104 4.7.4 TIME-DEFERRED CALCULATION OF THE VARIABLE PHASE (OPTIONAL) /
107 4.8 LOOP GAIN FACTOR / 109 4.8.1 PHASE-ERROR DYNAMIC RANGE / 111 4.9
PHASE-DOMAIN ADPLL ARCHITECTURE / 112 4.9.1 CLOSE-IN SPURS DUE TO
INJECTION PULLING / 114 4.10 PLL FREQUENCY RESPONSE / 115 4.10.1
CONVERSION BETWEEN THE S- AND Z-DOMAINS / 119 4.11 NOISE AND ERROR
SOURCES / 119 4.11.1 TDC RESOLUTION EFFECT ON PHASE NOISE / 120 4.11.2
PHASE NOISE DUE TO DCO SA DITHERING / 122 4.12 TYPELL ADPLL / 127 4.12.1
PLL FREQUENCY RESPONSE OF A TYPE II LOOP / 130 4.13 HIGHER-ORDER ADPLL /
133 4.13.1 PLL STABILITY ANALYSIS / 136 4.14 NONLINEAR DIFFERENTIAL TERM
OF AN ADPLL / 139 4.14.1 QUALITY MONITORING OF AN RF CLOCK / 140 4.15
DCO GAIN ESTIMATION USING A PLL / 141 4.16 GEAR SHIFTING OF PLL GAIN /
142 4.16.1 AUTONOMOUS GEAR-SHIFTING MECHANISM / 143 4.16.2 EXTENDED
GEAR-SHIFTING SCHEME WITH ZERO-PHASE RESTART / 148 4.17 EDGE SKIPPING
DITHERING SCHEME (OPTIONAL) / 154 4.18 SUMMARY / 155 X CONTENTS 5
APPLICATION: ADPLL-BASED TRANSMITTER 156 5.1 DIRECT FREQUENCY MODULATION
OF A DCO / 157 5.1.1 DISCRETE-TIME FREQUENCY MODULATION / 158 5.1.2
HYBRID OF PREDICTIVE/CLOSED PLL OPERATION / 158 5.1.3 EFFECT OF FREF/CKR
CLOCK MISALIGNMENT / 163 5.2 JUST-IN-TIME DCO GAIN CALCULATION / 164 5.3
GFSK PULSE SHAPING OF TRANSMITTER DATA / 167 5.3.1 INTERPOLATIVE FILTER
OPERATION / 172 5.4 POWER AMPLIFIER / 175 5.5 DIGITAL AMPLITUDE
MODULATION / 177 5.5.1 DISCRETE PULSE-SLIMMING CONTROL / 180 5.5.2
REGULATION OF TRANSMITTING POWER / 181 5.5.3 TUNING WORD ADJUSTMENT /
182 5.5.4 FULLY DIGITAL AMPLITUDE CONTROL / 183 5.6 GOING FORWARD: POLAR
TRANSMITTER / 183 5.6.1 GENERIC MODULATOR / 186 5.6.2 POLAR TX
REALIZATION / 187 5.7 SUMMARY / 188 6 BEHAVIORAL MODELING AND SIMULATION
189 6.1 SIMULATION METHODOLOGY / 190 6.2 DIGITAL BLOCKS / 191 6.3
SUPPORT OF DIGITAL STREAM PROCESSING / 192 6.4 RANDOM NUMBER GENERATOR /
192 6.5 TIME-DOMAIN MODELING OF DCO PHASE NOISE / 192 6.5.1 MODELING
OSCILLATOR JITTER / 192 6.5.2 MODELING OSCILLATOR WANDER / 194 6.5.3
MODELING OSCILLATOR FLICKER (1//) NOISE / 195 6.5.4 CLOCK EDGE DIVIDER
EFFECTS / 200 6.5.5 VHDL MODEL REALIZATION OF A DCO / 201 6.5.6 SUPPORT
OF PHYSICAL K OCO / 202 6.6 MODELING METASTABILITY IN FLIP-FLOPS / 203
6.7 SIMULATION RESULTS / 206 6.7.1 TIME-DOMAIN SIMULATIONS / 206 6.7.2
FREQUENCY-DEVIATION SIMULATIONS / 207 6.7.3 PHASE-DOMAIN SIMULATIONS OF
TRANSMITTERS / 209 6.7.4 SYNTHESIZER PHASE-NOISE SIMULATIONS / 209 6.8
SUMMARY / 212 CONTENTS XI 7 IMPLEMENTATION AND EXPERIMENTAL RESULTS 213
7.1 DSP AND ITS RF INTERFACE TO DRP / 213 7.2 TRANSMITTER CORE
IMPLEMENTATION / 214 7.3 IC CHIP / 216 7.4 EVALUATION BOARD / 218 7.5
MEASUREMENT EQUIPMENT / 218 7.6 GFSK TRANSMITTER PERFORMANCE / 219 7.7
SYNTHESIZER PERFORMANCE / 221 7.8 SYNTHESIZER SWITCHING TRANSIENTS / 224
7.9 DSP-DRIVEN MODULATION / 225 7.10 PERFORMANCE SUMMARY / 226 7.11
SUMMARY / 227 APPENDIX A: SPURS DUE TO DCO SWITCHING 228 A.L SPURS DUE
TO DCO MODULATION / 229 APPENDIX B: GAUSSIAN PULSE-SHAPING FILTER 232
APPENDIX C: VHDL SOURCE CODE 237 C.L DCO LEVEL 2 / 237 C.2
PERIOD-CONTROLLED OSCILLATOR / 239 C.3 TACTICAL FLIP-FLOP / 241 C.4 TDC
PSEUDO-THERMOMETER OUTPUT DECODER / 243 REFERENCES 247 INDEX 253
|
| any_adam_object | 1 |
| author | Staszewski, Robert Bogdan Balsara, Poras T. |
| author_facet | Staszewski, Robert Bogdan Balsara, Poras T. |
| author_role | aut aut |
| author_sort | Staszewski, Robert Bogdan |
| author_variant | r b s rb rbs p t b pt ptb |
| building | Verbundindex |
| bvnumber | BV023801518 |
| ctrlnum | (OCoLC)62858087 (DE-599)BVBBV023801518 |
| dewey-full | 621.3815/486 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815/486 |
| dewey-search | 621.3815/486 |
| dewey-sort | 3621.3815 3486 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01582nam a2200373zc 4500</leader><controlfield tag="001">BV023801518</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20111117 </controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">070724s2006 xx ad|| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780471772552</subfield><subfield code="9">978-0-471-77255-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)62858087</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV023801518</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield><subfield code="a">DE-29T</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815/486</subfield><subfield code="2">22</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Staszewski, Robert Bogdan</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">All-digital frequency synthesizer in deep-submicron CMOS</subfield><subfield code="c">Robert Bogdan Staszewski ; Poras T. Balsara</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Hoboken, NJ</subfield><subfield code="b">Wiley-Interscience</subfield><subfield code="c">2006</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XVII, 261 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Synthesizer</subfield><subfield code="g">Elektronik</subfield><subfield code="0">(DE-588)4184253-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CMOS</subfield><subfield code="0">(DE-588)4010319-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Synthesizer</subfield><subfield code="g">Elektronik</subfield><subfield code="0">(DE-588)4184253-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">CMOS</subfield><subfield code="0">(DE-588)4010319-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Balsara, Poras T.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://deposit.dnb.de/cgi-bin/dokserv?id=2846002&prov=M&dok_var=1&dok_ext=htm</subfield><subfield code="3">Beschreibung für Leser</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/toc/fy0705/2006040508.html</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">GBV Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017443717&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-017443717</subfield></datafield></record></collection> |
| id | DE-604.BV023801518 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T13:34:25Z |
| institution | BVB |
| isbn | 9780471772552 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017443717 |
| oclc_num | 62858087 |
| open_access_boolean | |
| owner | DE-634 DE-29T |
| owner_facet | DE-634 DE-29T |
| physical | XVII, 261 S. Ill., graph. Darst. |
| publishDate | 2006 |
| publishDateSearch | 2006 |
| publishDateSort | 2006 |
| publisher | Wiley-Interscience |
| record_format | marc |
| spellingShingle | Staszewski, Robert Bogdan Balsara, Poras T. All-digital frequency synthesizer in deep-submicron CMOS Synthesizer Elektronik (DE-588)4184253-4 gnd CMOS (DE-588)4010319-5 gnd |
| subject_GND | (DE-588)4184253-4 (DE-588)4010319-5 |
| title | All-digital frequency synthesizer in deep-submicron CMOS |
| title_auth | All-digital frequency synthesizer in deep-submicron CMOS |
| title_exact_search | All-digital frequency synthesizer in deep-submicron CMOS |
| title_full | All-digital frequency synthesizer in deep-submicron CMOS Robert Bogdan Staszewski ; Poras T. Balsara |
| title_fullStr | All-digital frequency synthesizer in deep-submicron CMOS Robert Bogdan Staszewski ; Poras T. Balsara |
| title_full_unstemmed | All-digital frequency synthesizer in deep-submicron CMOS Robert Bogdan Staszewski ; Poras T. Balsara |
| title_short | All-digital frequency synthesizer in deep-submicron CMOS |
| title_sort | all digital frequency synthesizer in deep submicron cmos |
| topic | Synthesizer Elektronik (DE-588)4184253-4 gnd CMOS (DE-588)4010319-5 gnd |
| topic_facet | Synthesizer Elektronik CMOS |
| url | http://deposit.dnb.de/cgi-bin/dokserv?id=2846002&prov=M&dok_var=1&dok_ext=htm http://www.loc.gov/catdir/toc/fy0705/2006040508.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017443717&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT staszewskirobertbogdan alldigitalfrequencysynthesizerindeepsubmicroncmos AT balsaraporast alldigitalfrequencysynthesizerindeepsubmicroncmos |