HDL chip design: a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Madison, AL
Donne Publ.
2000
|
| Edition: | 8. printing, minor revisions |
| Subjects: | |
| Physical Description: | XVI, 448 S. graph. Darst. |
| ISBN: | 0965193438 |
Staff View
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV023694085 | ||
| 003 | DE-604 | ||
| 005 | 20020111000000.0 | ||
| 007 | t| | ||
| 008 | 010710s2000 xxud||| |||| 00||| eng d | ||
| 020 | |a 0965193438 |c DM 160.00 |9 0-9651934-3-8 | ||
| 035 | |a (OCoLC)915832354 | ||
| 035 | |a (DE-599)BVBBV023694085 | ||
| 040 | |a DE-604 |b ger | ||
| 041 | 0 | |a eng | |
| 044 | |a xxu |c US | ||
| 049 | |a DE-522 |a DE-83 | ||
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 100 | 1 | |a Smith, Douglas J. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a HDL chip design |b a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog |c Douglas J. Smith. Forew. by Alex Zamfirescu |
| 250 | |a 8. printing, minor revisions | ||
| 264 | 1 | |a Madison, AL |b Donne Publ. |c 2000 | |
| 300 | |a XVI, 448 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 2 | |5 DE-604 | |
| 689 | 3 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 3 | |5 DE-604 | |
| 689 | 4 | 0 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |D s |
| 689 | 4 | |8 1\p |5 DE-604 | |
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-017194649 | |
Record in the Search Index
| _version_ | 1818966248725151744 |
|---|---|
| any_adam_object | |
| author | Smith, Douglas J. |
| author_facet | Smith, Douglas J. |
| author_role | aut |
| author_sort | Smith, Douglas J. |
| author_variant | d j s dj djs |
| building | Verbundindex |
| bvnumber | BV023694085 |
| classification_rvk | ST 250 |
| ctrlnum | (OCoLC)915832354 (DE-599)BVBBV023694085 |
| discipline | Informatik |
| edition | 8. printing, minor revisions |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01789nam a2200481zc 4500</leader><controlfield tag="001">BV023694085</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20020111000000.0</controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">010710s2000 xxud||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0965193438</subfield><subfield code="c">DM 160.00</subfield><subfield code="9">0-9651934-3-8</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)915832354</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV023694085</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">xxu</subfield><subfield code="c">US</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-522</subfield><subfield code="a">DE-83</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 250</subfield><subfield code="0">(DE-625)143626:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Smith, Douglas J.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">HDL chip design</subfield><subfield code="b">a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog</subfield><subfield code="c">Douglas J. Smith. Forew. by Alex Zamfirescu</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">8. printing, minor revisions</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Madison, AL</subfield><subfield code="b">Donne Publ.</subfield><subfield code="c">2000</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XVI, 448 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Kundenspezifische Schaltung</subfield><subfield code="0">(DE-588)4122250-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Hardwarebeschreibungssprache</subfield><subfield code="0">(DE-588)4159102-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Kundenspezifische Schaltung</subfield><subfield code="0">(DE-588)4122250-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="3" ind2="0"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="4" ind2="0"><subfield code="a">Hardwarebeschreibungssprache</subfield><subfield code="0">(DE-588)4159102-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="4" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-017194649</subfield></datafield></record></collection> |
| id | DE-604.BV023694085 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T13:29:53Z |
| institution | BVB |
| isbn | 0965193438 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017194649 |
| oclc_num | 915832354 |
| open_access_boolean | |
| owner | DE-522 DE-83 |
| owner_facet | DE-522 DE-83 |
| physical | XVI, 448 S. graph. Darst. |
| publishDate | 2000 |
| publishDateSearch | 2000 |
| publishDateSort | 2000 |
| publisher | Donne Publ. |
| record_format | marc |
| spelling | Smith, Douglas J. Verfasser aut HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith. Forew. by Alex Zamfirescu 8. printing, minor revisions Madison, AL Donne Publ. 2000 XVI, 448 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Hardwarebeschreibungssprache (DE-588)4159102-1 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 s DE-604 Field programmable gate array (DE-588)4347749-5 s VHDL (DE-588)4254792-1 s VERILOG (DE-588)4268385-3 s Hardwarebeschreibungssprache (DE-588)4159102-1 s 1\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Smith, Douglas J. HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog Kundenspezifische Schaltung (DE-588)4122250-7 gnd VHDL (DE-588)4254792-1 gnd Field programmable gate array (DE-588)4347749-5 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4122250-7 (DE-588)4254792-1 (DE-588)4347749-5 (DE-588)4159102-1 (DE-588)4268385-3 |
| title | HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_auth | HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_exact_search | HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_full | HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith. Forew. by Alex Zamfirescu |
| title_fullStr | HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith. Forew. by Alex Zamfirescu |
| title_full_unstemmed | HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith. Forew. by Alex Zamfirescu |
| title_short | HDL chip design |
| title_sort | hdl chip design a practical guide for designing syntheszing and simulating asics and fpgas using vhdl or verilog |
| title_sub | a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog |
| topic | Kundenspezifische Schaltung (DE-588)4122250-7 gnd VHDL (DE-588)4254792-1 gnd Field programmable gate array (DE-588)4347749-5 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Kundenspezifische Schaltung VHDL Field programmable gate array Hardwarebeschreibungssprache VERILOG |
| work_keys_str_mv | AT smithdouglasj hdlchipdesignapracticalguidefordesigningsyntheszingandsimulatingasicsandfpgasusingvhdlorverilog |