HDL chip design: a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog
Gespeichert in:
| Beteilige Person: | |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Madison, AL
Donne Publ.
2000
|
| Ausgabe: | 8. printing, minor revisions |
| Schlagwörter: | |
| Umfang: | XVI, 448 S. graph. Darst. |
| ISBN: | 0965193438 |
Internformat
MARC
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| 040 | |a DE-604 |b ger | ||
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| 100 | 1 | |a Smith, Douglas J. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a HDL chip design |b a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog |c Douglas J. Smith. Forew. by Alex Zamfirescu |
| 250 | |a 8. printing, minor revisions | ||
| 264 | 1 | |a Madison, AL |b Donne Publ. |c 2000 | |
| 300 | |a XVI, 448 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
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Datensatz im Suchindex
| _version_ | 1818966248725151744 |
|---|---|
| any_adam_object | |
| author | Smith, Douglas J. |
| author_facet | Smith, Douglas J. |
| author_role | aut |
| author_sort | Smith, Douglas J. |
| author_variant | d j s dj djs |
| building | Verbundindex |
| bvnumber | BV023694085 |
| classification_rvk | ST 250 |
| ctrlnum | (OCoLC)915832354 (DE-599)BVBBV023694085 |
| discipline | Informatik |
| edition | 8. printing, minor revisions |
| format | Book |
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| id | DE-604.BV023694085 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T13:29:53Z |
| institution | BVB |
| isbn | 0965193438 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017194649 |
| oclc_num | 915832354 |
| open_access_boolean | |
| owner | DE-522 DE-83 |
| owner_facet | DE-522 DE-83 |
| physical | XVI, 448 S. graph. Darst. |
| publishDate | 2000 |
| publishDateSearch | 2000 |
| publishDateSort | 2000 |
| publisher | Donne Publ. |
| record_format | marc |
| spelling | Smith, Douglas J. Verfasser aut HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith. Forew. by Alex Zamfirescu 8. printing, minor revisions Madison, AL Donne Publ. 2000 XVI, 448 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Hardwarebeschreibungssprache (DE-588)4159102-1 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 s DE-604 Field programmable gate array (DE-588)4347749-5 s VHDL (DE-588)4254792-1 s VERILOG (DE-588)4268385-3 s Hardwarebeschreibungssprache (DE-588)4159102-1 s 1\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Smith, Douglas J. HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog Kundenspezifische Schaltung (DE-588)4122250-7 gnd VHDL (DE-588)4254792-1 gnd Field programmable gate array (DE-588)4347749-5 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4122250-7 (DE-588)4254792-1 (DE-588)4347749-5 (DE-588)4159102-1 (DE-588)4268385-3 |
| title | HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_auth | HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_exact_search | HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_full | HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith. Forew. by Alex Zamfirescu |
| title_fullStr | HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith. Forew. by Alex Zamfirescu |
| title_full_unstemmed | HDL chip design a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith. Forew. by Alex Zamfirescu |
| title_short | HDL chip design |
| title_sort | hdl chip design a practical guide for designing syntheszing and simulating asics and fpgas using vhdl or verilog |
| title_sub | a practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog |
| topic | Kundenspezifische Schaltung (DE-588)4122250-7 gnd VHDL (DE-588)4254792-1 gnd Field programmable gate array (DE-588)4347749-5 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Kundenspezifische Schaltung VHDL Field programmable gate array Hardwarebeschreibungssprache VERILOG |
| work_keys_str_mv | AT smithdouglasj hdlchipdesignapracticalguidefordesigningsyntheszingandsimulatingasicsandfpgasusingvhdlorverilog |