APA-Zitierstil (7. Ausg.)

Smith, D. J. (2000). HDL chip design: A practical guide for designing, syntheszing and simulating ASICs and FPGAs using VHDL or Verilog (8. printing, minor revisions.). Donne Publ.

Chicago-Zitierstil (17. Ausg.)

Smith, Douglas J. HDL Chip Design: A Practical Guide for Designing, Syntheszing and Simulating ASICs and FPGAs Using VHDL or Verilog. 8. printing, minor revisions. Madison, AL: Donne Publ, 2000.

MLA-Zitierstil (9. Ausg.)

Smith, Douglas J. HDL Chip Design: A Practical Guide for Designing, Syntheszing and Simulating ASICs and FPGAs Using VHDL or Verilog. 8. printing, minor revisions. Donne Publ, 2000.