Sensitivity and optimization:
Gespeichert in:
| Beteiligte Personen: | , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Amsterdam [u.a.]
Elsevier
1980
|
| Schriftenreihe: | Computer-aided design of electronic circuits
2 |
| Schlagwörter: | |
| Umfang: | XII, 368 S. |
| ISBN: | 0444419292 |
Internformat
MARC
| LEADER | 00000nam a2200000zcb4500 | ||
|---|---|---|---|
| 001 | BV022011791 | ||
| 003 | DE-604 | ||
| 005 | 20040229000000.0 | ||
| 007 | t| | ||
| 008 | 870709s1980 xx |||| 00||| eng d | ||
| 020 | |a 0444419292 |9 0-444-41929-2 | ||
| 035 | |a (OCoLC)6735434 | ||
| 035 | |a (DE-599)BVBBV022011791 | ||
| 040 | |a DE-604 |b ger | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-706 | ||
| 050 | 0 | |a TK7867 | |
| 082 | 0 | |a 621.3815/3 |2 19 | |
| 084 | |a SK 950 |0 (DE-625)143273: |2 rvk | ||
| 100 | 1 | |a Brayton, Robert K. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Sensitivity and optimization |c Robert K. Brayton ; Robert Spence |
| 264 | 1 | |a Amsterdam [u.a.] |b Elsevier |c 1980 | |
| 300 | |a XII, 368 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Computer-aided design of electronic circuits |v 2 | |
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Electronic circuit design |x Data processing | |
| 650 | 0 | 7 | |a Simulation |0 (DE-588)4055072-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Netzwerkanalyse |0 (DE-588)4075298-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Sensitivitätsanalyse |0 (DE-588)4129730-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CAD |0 (DE-588)4069794-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Simulation |0 (DE-588)4055072-2 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a CAD |0 (DE-588)4069794-0 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a Netzwerkanalyse |0 (DE-588)4075298-7 |D s |
| 689 | 2 | |5 DE-604 | |
| 689 | 3 | 0 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 3 | |5 DE-604 | |
| 689 | 4 | 0 | |a Logischer Entwurf |0 (DE-588)4168051-0 |D s |
| 689 | 4 | 1 | |a Sensitivitätsanalyse |0 (DE-588)4129730-1 |D s |
| 689 | 4 | |8 1\p |5 DE-604 | |
| 700 | 1 | |a Spence, Robert |e Verfasser |4 aut | |
| 830 | 0 | |a Computer-aided design of electronic circuits |v 2 |w (DE-604)BV021844930 | |
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-015226424 | |
Datensatz im Suchindex
| _version_ | 1818963535091204096 |
|---|---|
| any_adam_object | |
| author | Brayton, Robert K. Spence, Robert |
| author_facet | Brayton, Robert K. Spence, Robert |
| author_role | aut aut |
| author_sort | Brayton, Robert K. |
| author_variant | r k b rk rkb r s rs |
| building | Verbundindex |
| bvnumber | BV022011791 |
| callnumber-first | T - Technology |
| callnumber-label | TK7867 |
| callnumber-raw | TK7867 |
| callnumber-search | TK7867 |
| callnumber-sort | TK 47867 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | SK 950 |
| ctrlnum | (OCoLC)6735434 (DE-599)BVBBV022011791 |
| dewey-full | 621.3815/3 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815/3 |
| dewey-search | 621.3815/3 |
| dewey-sort | 3621.3815 13 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Mathematik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02003nam a2200565zcb4500</leader><controlfield tag="001">BV022011791</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20040229000000.0</controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">870709s1980 xx |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0444419292</subfield><subfield code="9">0-444-41929-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)6735434</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV022011791</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-706</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7867</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815/3</subfield><subfield code="2">19</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">SK 950</subfield><subfield code="0">(DE-625)143273:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Brayton, Robert K.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Sensitivity and optimization</subfield><subfield code="c">Robert K. Brayton ; Robert Spence</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Amsterdam [u.a.]</subfield><subfield code="b">Elsevier</subfield><subfield code="c">1980</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XII, 368 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Computer-aided design of electronic circuits</subfield><subfield code="v">2</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Datenverarbeitung</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuit design</subfield><subfield code="x">Data processing</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Simulation</subfield><subfield code="0">(DE-588)4055072-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Netzwerkanalyse</subfield><subfield code="0">(DE-588)4075298-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Sensitivitätsanalyse</subfield><subfield code="0">(DE-588)4129730-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Simulation</subfield><subfield code="0">(DE-588)4055072-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Netzwerkanalyse</subfield><subfield code="0">(DE-588)4075298-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="3" ind2="0"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="4" ind2="0"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="4" ind2="1"><subfield code="a">Sensitivitätsanalyse</subfield><subfield code="0">(DE-588)4129730-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="4" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Spence, Robert</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Computer-aided design of electronic circuits</subfield><subfield code="v">2</subfield><subfield code="w">(DE-604)BV021844930</subfield><subfield code="9"></subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-015226424</subfield></datafield></record></collection> |
| id | DE-604.BV022011791 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T12:46:45Z |
| institution | BVB |
| isbn | 0444419292 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015226424 |
| oclc_num | 6735434 |
| open_access_boolean | |
| owner | DE-706 |
| owner_facet | DE-706 |
| physical | XII, 368 S. |
| publishDate | 1980 |
| publishDateSearch | 1980 |
| publishDateSort | 1980 |
| publisher | Elsevier |
| record_format | marc |
| series | Computer-aided design of electronic circuits |
| series2 | Computer-aided design of electronic circuits |
| spelling | Brayton, Robert K. Verfasser aut Sensitivity and optimization Robert K. Brayton ; Robert Spence Amsterdam [u.a.] Elsevier 1980 XII, 368 S. txt rdacontent n rdamedia nc rdacarrier Computer-aided design of electronic circuits 2 Datenverarbeitung Electronic circuit design Data processing Simulation (DE-588)4055072-2 gnd rswk-swf Netzwerkanalyse (DE-588)4075298-7 gnd rswk-swf Sensitivitätsanalyse (DE-588)4129730-1 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf Simulation (DE-588)4055072-2 s DE-604 CAD (DE-588)4069794-0 s Netzwerkanalyse (DE-588)4075298-7 s Schaltungsentwurf (DE-588)4179389-4 s Logischer Entwurf (DE-588)4168051-0 s Sensitivitätsanalyse (DE-588)4129730-1 s 1\p DE-604 Spence, Robert Verfasser aut Computer-aided design of electronic circuits 2 (DE-604)BV021844930 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Brayton, Robert K. Spence, Robert Sensitivity and optimization Computer-aided design of electronic circuits Datenverarbeitung Electronic circuit design Data processing Simulation (DE-588)4055072-2 gnd Netzwerkanalyse (DE-588)4075298-7 gnd Sensitivitätsanalyse (DE-588)4129730-1 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4055072-2 (DE-588)4075298-7 (DE-588)4129730-1 (DE-588)4179389-4 (DE-588)4168051-0 (DE-588)4069794-0 |
| title | Sensitivity and optimization |
| title_auth | Sensitivity and optimization |
| title_exact_search | Sensitivity and optimization |
| title_full | Sensitivity and optimization Robert K. Brayton ; Robert Spence |
| title_fullStr | Sensitivity and optimization Robert K. Brayton ; Robert Spence |
| title_full_unstemmed | Sensitivity and optimization Robert K. Brayton ; Robert Spence |
| title_short | Sensitivity and optimization |
| title_sort | sensitivity and optimization |
| topic | Datenverarbeitung Electronic circuit design Data processing Simulation (DE-588)4055072-2 gnd Netzwerkanalyse (DE-588)4075298-7 gnd Sensitivitätsanalyse (DE-588)4129730-1 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd CAD (DE-588)4069794-0 gnd |
| topic_facet | Datenverarbeitung Electronic circuit design Data processing Simulation Netzwerkanalyse Sensitivitätsanalyse Schaltungsentwurf Logischer Entwurf CAD |
| volume_link | (DE-604)BV021844930 |
| work_keys_str_mv | AT braytonrobertk sensitivityandoptimization AT spencerobert sensitivityandoptimization |