The hierarchical analysis of VLSI designs:
Gespeichert in:
| Beteilige Person: | |
|---|---|
| Format: | Buch |
| Sprache: | Nichtbestimmte Sprache |
| Veröffentlicht: |
1984
|
| Schlagwörter: | |
| Beschreibung: | New York, N.Y., Univ., Diss., 1983 |
| Umfang: | II, 170 S. |
Internformat
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Datensatz im Suchindex
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| author | Hon, Robert W. |
| author_facet | Hon, Robert W. |
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| author_sort | Hon, Robert W. |
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| id | DE-604.BV021875819 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T12:43:55Z |
| institution | BVB |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015091463 |
| oclc_num | 634018740 |
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| owner_facet | DE-706 |
| physical | II, 170 S. |
| publishDate | 1984 |
| publishDateSearch | 1984 |
| publishDateSort | 1984 |
| record_format | marc |
| spelling | Hon, Robert W. Verfasser aut The hierarchical analysis of VLSI designs 1984 II, 170 S. txt rdacontent n rdamedia nc rdacarrier New York, N.Y., Univ., Diss., 1983 Hierarchisches System (DE-588)4159833-7 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Verifikation (DE-588)4135577-5 gnd rswk-swf Analyse (DE-588)4122795-5 gnd rswk-swf VLSI (DE-588)4117388-0 s DE-604 Analyse (DE-588)4122795-5 s Verifikation (DE-588)4135577-5 s Hierarchisches System (DE-588)4159833-7 s |
| spellingShingle | Hon, Robert W. The hierarchical analysis of VLSI designs Hierarchisches System (DE-588)4159833-7 gnd VLSI (DE-588)4117388-0 gnd Verifikation (DE-588)4135577-5 gnd Analyse (DE-588)4122795-5 gnd |
| subject_GND | (DE-588)4159833-7 (DE-588)4117388-0 (DE-588)4135577-5 (DE-588)4122795-5 |
| title | The hierarchical analysis of VLSI designs |
| title_auth | The hierarchical analysis of VLSI designs |
| title_exact_search | The hierarchical analysis of VLSI designs |
| title_full | The hierarchical analysis of VLSI designs |
| title_fullStr | The hierarchical analysis of VLSI designs |
| title_full_unstemmed | The hierarchical analysis of VLSI designs |
| title_short | The hierarchical analysis of VLSI designs |
| title_sort | the hierarchical analysis of vlsi designs |
| topic | Hierarchisches System (DE-588)4159833-7 gnd VLSI (DE-588)4117388-0 gnd Verifikation (DE-588)4135577-5 gnd Analyse (DE-588)4122795-5 gnd |
| topic_facet | Hierarchisches System VLSI Verifikation Analyse |
| work_keys_str_mv | AT honrobertw thehierarchicalanalysisofvlsidesigns |