Verfügbarkeit: Fast, efficient and predictable memory accesses

Fast, efficient and predictable memory accesses: optimization algorithms for memory architecture aware compilation

Gespeichert in:

Bibliographische Detailangaben
Beteilige Person:	Wehmeyer, Lars (VerfasserIn)
Format:	Hochschulschrift/Dissertation Buch
Sprache:	Englisch
Veröffentlicht:	2005
Schlagwörter:	Speicherverwaltung Hochschulschrift
Links:	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014850078&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
Umfang:	XVI, 288 S. graph. Darst. 30 cm

Internformat

MARC


LEADER	00000nam a2200000 c 4500
001	BV021635227
003	DE-604
005	20060718
007	t\|
008	060629s2005 gw d\|\|\| m\|\|\| 00\|\|\| eng d
015			\|a 06,H06,0061 \|2 dnb
016	7		\|a 979305128 \|2 DE-101
035			\|a (OCoLC)166032976
035			\|a (DE-599)BVBBV021635227
040			\|a DE-604 \|b ger \|e rakddb
041	0		\|a eng
044			\|a gw \|c XA-DE
049			\|a DE-355 \|a DE-91G \|a DE-12 \|a DE-83 \|a DE-188
082	0		\|a 005.435 \|2 22/ger
082	0		\|a 004.5 \|2 22/ger
084			\|a ST 175 \|0 (DE-625)143603: \|2 rvk
084			\|a DAT 406d \|2 stub
084			\|a 004 \|2 sdnb
100	1		\|a Wehmeyer, Lars \|e Verfasser \|4 aut
245	1	0	\|a Fast, efficient and predictable memory accesses \|b optimization algorithms for memory architecture aware compilation \|c von Lars Wehmeyer
264		1	\|c 2005
300			\|a XVI, 288 S. \|b graph. Darst. \|c 30 cm
336			\|b txt \|2 rdacontent
337			\|b n \|2 rdamedia
338			\|b nc \|2 rdacarrier
502			\|a Dortmund, Univ., Diss., 2005
650	0	7	\|a Speicherverwaltung \|0 (DE-588)4182146-4 \|2 gnd \|9 rswk-swf
655		7	\|0 (DE-588)4113937-9 \|a Hochschulschrift \|2 gnd-content
689	0	0	\|a Speicherverwaltung \|0 (DE-588)4182146-4 \|D s
689	0		\|5 DE-604
856	4	2	\|m DNB Datenaustausch \|q application/pdf \|u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014850078&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA \|3 Inhaltsverzeichnis
943	1		\|a oai:aleph.bib-bvb.de:BVB01-014850078

Datensatz im Suchindex

DE-BY-TUM_call_number	0109 2006 B 2035
DE-BY-TUM_katkey	1555668
DE-BY-TUM_location	01
DE-BY-TUM_media_number	040010241555
_version_	1821933189501812736
adam_text	FAST, EFFICIENT AND PREDICTABLE MEMORY ACCESSES OPTIMIZATION ALGORITHMS FOR MEMORY ARCHITECTURE AWARE COMPILATION DISSERTATION ZUR ERLANGUNG DES GRADES EINES DOKTOR S DE R NATU R W I SSENSCHAFTE N DER UNIVERSITAT DORTMUND AM FACHBEREICH INFORMATIK VON LARS WEHMEYER DORTMUND 2005 ULB DARMSTADT ILLLLLLLLLLLLLLLLLL L 16323551 CONTENTS DEDICATION III LIST OF FIGURES IX LIST OF TABLES XVI ACKNOWLEDGMENTS XVII 1. ABSTRACT 1 2. INTRODUCTION 3 2.1 MOTIVATION 6 2.2 CONTRIBUTIONS OF THIS WORK 11 2.3 OVERVIEW 14 3. MODELS AND TOOLS 17 3.1 INSTRUCTION SET ARCHITECTURE MODELS 19 3.1.1 ARMV4T 19 3.1.2 SPARC V8 21 3.2 MEMORY MODELS 24 3.2.1 SRAM 25 3.2.2 DRAM 27 3.2.3 FLASH MEMORY 30 3.2.4 CACHES 31 3.3 TIMING MODELS 35 3.3.1 PROCESSOR TIMING 35 3.3.1.1 ARM7TDMI INSTRUCTION TIMING 36 3.3.1.2 LEON INSTRUCTION TIMING 38 3.3.2 MEMORY TIMING 40 3.3.2.1 SRAM TIMING MODEL 40 3.3.2.2 DRAM TIMING MODEL 42 VI 3.3.2.3 FLASH MEMORY TIMING MODEL 44 3.3.2.4 CACHE TIMING MODEL 45 3.4 ENERGY MODELS 46 3.4.1 SOURCES OF ENERGY DISSIPATION 47 3.4.2 PROCESSOR ENERGY 49 3.4.2.1 RELATED WORK 49 3.4.2.2 ARM7 ENERGY MODEL 54 3.4.2.3 LEON ENERGY MODEL 54 3.4.3 MEMORY ENERGY 62 3.4.3.1 RELATED WORK 63 3.4.3.2 SRAM ENERGY MODEL 66 3.4.3.3 DRAM ENERGY MODEL 69 3.4.3.4 FLASH MEMORY ENERGY MODEL 78 3.4.3.5 CACHE ENERGY MODEL 79 3.5 SIMULATION MODELS 80 3.5.1 PROCESSOR SIMULATION MODELS 81 3.5.1.1 RELATED WORK 81 3.5.1.2 ARM7 SIMULATION MODEL 84 3.5.1.3 LEON SIMULATION MODEL 85 3.5.2 MEMORY SIMULATION MODEL 87 3.5.2.1 RELATED WORK 88 3.5.2.2 TECHNICAL REQUIREMENTS 89 3.5.2.3 WORKFLOW 90 3.5.2.4 SIMULATION KERNEL 92 3.5.2.5 COMPONENTS 93 3.5.2.6 CONFIGURATION 97 3.6 THE ENCC COMPILER FRAMEWORK 98 3.6.1 WORKFLOW 99 3.6.2 ENPROFILER 103 3.6.3 MEMORY ARCHITECTURE AWARE COMPILATION 105 4. SCRATCHPAD MEMORY OPTIMIZATIONS 113 4.1 RELATED WORK 115 4.2 MULTI MEMORY OPTIMIZATION 121 4.2.1 MEMORY OBJECTS 123 4.2.2 PREREQUISITES 124 4.2.3 ENERGY FUNCTIONS 125 4.2.4 THE BASE MODEL 126 4.2.5 THE TOP-DOWN MODEL 128 CONTENTS VII 4.2.6 THE BOTTOM-UP MODEL 136 4.2.7 THE ARM TCM MODEL 140 4.2.8 LEAKAGE-ENERGY AWARE MEMORY CONFIGURATION 142 4.2.9 RESULTS FOR MULTI MEMORY OPTIMIZATION 145 4.2.9.1 COMPARISON OF BASE, TOP-DOWN AND BOTTOM-UP 148 4.2.9.2 RESULTS FOR THE ARM TCM ARCHITECTURE 156 4.2.9.3 RESULTS FOR COMPILER GUIDED MEMORY CONFIGURATION 159 4.3 IMPACT OF SCRATCHPAD ALLOCATION TECHNIQUES ON WCET 162 4.3.1 RELATED WORK 165 4.3.2 TOOLS AND WORKFLOW 168 4.3.3 REQUIRED ANNOTATION INFORMATION 171 4.3.4 BENCHMARKS AND MEMORY HIERARCHY CONFIGURATION 177 4.3.5 WCET RESULTS FOR STATIC ALLOCATION 178 4.3.6 WCET RESULTS FOR DYNAMIC ALLOCATION 187 5. MAIN MEMORY OPTIMIZATIONS 197 5.1 RELATED WORK 198 5.2 MAIN MEMORY POWER MANAGEMENT 200 5.2.1 MOTIVATING EXAMPLE 203 5.2.2 PREREQUISITES 205 5.2.3 MEMORY OBJECTS AND ENERGY FUNCTIONS 205 5.2.4 BINARY DECISION VARIABLES 208 5.2.5 OBJECTIVE FUNCTION 210 5.2.6 CONSTRAINTS 211 5.2.7 RESULTS FOR MAIN MEMORY POWER MANAGEMENT 212 5.3 EXECUTE-IN-PLACE USING FLASH MEMORIES 218 5.3.1 ANALYSIS OF THE COPY FUNCTION 221 5.3.2 MAIN MEMORY PARTITIONING 222 5.3.3 PREREQUISITES 224 5.3.4 PRESELECTION OF MEMORY OBJECTS TO ENABLE DEEP POWER DOWN 226 5.3.5 FORMALIZATION OF THE PRESELECTION ALGORITHM 230 5.3.6 FORMALIZATION OF THE XIP ALLOCATION PROBLEM 232 5.3.6.1 DECISION VARIABLES 233 5.3.6.2 CONSTRAINTS 234 5.3.6.3 OBJECTIVE FUNCTION 234 5.3.7 RESULTS FOR XIP 235 VLL L 6. REGISTER FILE OPTIMIZATION 245 6.1 RELATED WORK 246 6.2 IMPLEMENTATION OF THE REGISTER FILE 247 6.3 REGISTER ALLOCATION AND LIFETIME ANALYSIS 248 6.4 WORKFLOW AND METHODOLOGY 250 6.5 BENCHMARK SUITE 252 6.5.1 RESULTS FOR THE RATIO OF SPILL CODE TO TOTAL CODE SIZE 253 6.5.2 RESULTS FOR THE NUMBER OF CYCLES 254 6.5.3 RESULTS FOR ENERGY CONSUMPTION 257 6.6 COMPILER GUIDED CHOICE OF REGISTER FILE SIZE 258 7. SUMMARY 261 8. FUTURE WORK 267 9. AUTHOR S CONTRIBUTIONS 271 9.1 CONTRIBUTIONS TO THE PH.D. THESIS 271 9.2 CONTRIBUTIONS TO THE LIST OF PUBLICATIONS 273 REFERENCES 277
any_adam_object	1
author	Wehmeyer, Lars
author_facet	Wehmeyer, Lars
author_role	aut
author_sort	Wehmeyer, Lars
author_variant	l w lw
building	Verbundindex
bvnumber	BV021635227
classification_rvk	ST 175
classification_tum	DAT 406d
ctrlnum	(OCoLC)166032976 (DE-599)BVBBV021635227
dewey-full	005.435 004.5
dewey-hundreds	000 - Computer science, information, general works
dewey-ones	005 - Computer programming, programs, data, security 004 - Computer science
dewey-raw	005.435 004.5
dewey-search	005.435 004.5
dewey-sort	15.435
dewey-tens	000 - Computer science, information, general works
discipline	Informatik
format	Thesis Book
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01520nam a2200409 c 4500</leader><controlfield tag="001">BV021635227</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20060718 </controlfield><controlfield tag="007">t\|</controlfield><controlfield tag="008">060629s2005 gw d\|\|\| m\|\|\| 00\|\|\| eng d</controlfield><datafield tag="015" ind1=" " ind2=" "><subfield code="a">06,H06,0061</subfield><subfield code="2">dnb</subfield></datafield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">979305128</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)166032976</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV021635227</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">gw</subfield><subfield code="c">XA-DE</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-355</subfield><subfield code="a">DE-91G</subfield><subfield code="a">DE-12</subfield><subfield code="a">DE-83</subfield><subfield code="a">DE-188</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">005.435</subfield><subfield code="2">22/ger</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">004.5</subfield><subfield code="2">22/ger</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 175</subfield><subfield code="0">(DE-625)143603:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 406d</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">004</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Wehmeyer, Lars</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Fast, efficient and predictable memory accesses</subfield><subfield code="b">optimization algorithms for memory architecture aware compilation</subfield><subfield code="c">von Lars Wehmeyer</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2005</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XVI, 288 S.</subfield><subfield code="b">graph. Darst.</subfield><subfield code="c">30 cm</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="502" ind1=" " ind2=" "><subfield code="a">Dortmund, Univ., Diss., 2005</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Speicherverwaltung</subfield><subfield code="0">(DE-588)4182146-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4113937-9</subfield><subfield code="a">Hochschulschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Speicherverwaltung</subfield><subfield code="0">(DE-588)4182146-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">DNB Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014850078&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-014850078</subfield></datafield></record></collection>
genre	(DE-588)4113937-9 Hochschulschrift gnd-content
genre_facet	Hochschulschrift
id	DE-604.BV021635227
illustrated	Illustrated
indexdate	2024-12-20T12:38:14Z
institution	BVB
language	English
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-014850078
oclc_num	166032976
open_access_boolean
owner	DE-355 DE-BY-UBR DE-91G DE-BY-TUM DE-12 DE-83 DE-188
owner_facet	DE-355 DE-BY-UBR DE-91G DE-BY-TUM DE-12 DE-83 DE-188
physical	XVI, 288 S. graph. Darst. 30 cm
publishDate	2005
publishDateSearch	2005
publishDateSort	2005
record_format	marc
spellingShingle	Wehmeyer, Lars Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation Speicherverwaltung (DE-588)4182146-4 gnd
subject_GND	(DE-588)4182146-4 (DE-588)4113937-9
title	Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation
title_auth	Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation
title_exact_search	Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation
title_full	Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation von Lars Wehmeyer
title_fullStr	Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation von Lars Wehmeyer
title_full_unstemmed	Fast, efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation von Lars Wehmeyer
title_short	Fast, efficient and predictable memory accesses
title_sort	fast efficient and predictable memory accesses optimization algorithms for memory architecture aware compilation
title_sub	optimization algorithms for memory architecture aware compilation
topic	Speicherverwaltung (DE-588)4182146-4 gnd
topic_facet	Speicherverwaltung Hochschulschrift
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014850078&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT wehmeyerlars fastefficientandpredictablememoryaccessesoptimizationalgorithmsformemoryarchitectureawarecompilation

Verfügbarkeit

Bestellen (Login erforderlich)

Inhaltsverzeichnis
Paper/Kapitel scannen lassen

Teilbibliothek Mathematik & Informatik, Dissertationen und Abschlussarbeiten

Bestandsangaben von Teilbibliothek Mathematik & Informatik, Dissertationen und Abschlussarbeiten
Signatur:	0109 2006 B 2035 Lageplan
Exemplar 1	Ausleihbar Am Standort