Verfügbarkeit: CMOS VLSI design | Technische Universität München

CMOS VLSI design: a circuits and systems perspective

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Bibliographische Detailangaben
Beteiligte Personen:	Weste, Neil H. E. (VerfasserIn), Harris, David Money 19XX- (VerfasserIn)
Format:	Buch
Sprache:	Englisch
Veröffentlicht:	Boston Pearson/Addison-Wesley 2005
Ausgabe:	3. ed., internat. ed.
Schlagwörter:	aIntegrated circuits > xVery large scale integration > xdesign and construction aMetal oxide semiconductors, Complementary CMOS-Schaltung VLSI
Links:	http://www.loc.gov/catdir/toc/ecip0416/2004007092.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013100770&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
Beschreibung:	Revision of: Principles of CMOS VLSI design. 1993. Includes bibliographical references (p. 927-952) and index
Umfang:	XXIV, 967 S. Ill., graph. Darst. 24 cm
ISBN:	0321149017 0321269772

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245	1	0	\|a CMOS VLSI design \|b a circuits and systems perspective \|c Neil H.E. Weste, David Harris
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500			\|a Revision of: Principles of CMOS VLSI design. 1993.
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Datensatz im Suchindex

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adam_text	CMOS VLSI DESIGN A CIRCUITS AND SYSTEMS THIRD EDITION F NEIL H. E. WESTE MACQUARIE UNIVERSITY AND THE UNIVERSITY OF ADELAIDE DAVID HARRIS HARVEY MUDD COLLEGE / . VIS . RIIFTIIF-I PEARSON ADDISON VS V BOSTON SAN FRANCISCO NEW YORK LONDON TORONTO SYDNEY TOKYO SINGAPORE MADRID MEXICO CITY MUNICH PARIS CAPE TOWN HONG KONG MONTREAL II CHAPTER 1 INTRODUCTION 1.1 A BRIEF HISTORY .. 1.2 BOOK SUMMARY . 1.3 MOS TRANSISTORS 1.4 CMOS LOGIC 10 14 .4.1 THE INVERTER 10 .4.2 THE NAND GATE 10 .4.3 COMBINATIONAL LOGIC 11 .4.4 THE NOR GATE 12 .4.5 COMPOUND GATES 13 .4.6 PASS TRANSISTORS AND TRANSMISSION GATES .4.7 TRISTATES 17 .4.8 MULTIPLEXERS 18 .4.9 LATCHES AND FLIP-FLOPS 20 1.5 CMOS FABRICATION AND LAYOUT 23 .5.1 INVERTER CROSS-SECTION 23 .5.2 FABRICATION PROCESS 24 .5.3 LAYOUT DESIGN RULES 28 .5.4 GATE LAYOUT 32 .5.5 STICK DIAGRAMS 33 1.6 DESIGN PARTITIONING 1.7 [^5J5J3\| A SIMPLE MIPS MICROPROCESSOR .. 1.7.1 MIPS ARCHITECTURE 39 1.7.2 MULTICYCLE MIPS MICROARCHITECTURE 42 1.8 LOGIC DESIGN 1.8.1 TOP-LEVEL INTERFACE 46 1.8.2 BLOCK DIAGRAM 47 1.8.3 HIERARCHY 47 1.8.4 HARDWARE DESCRIPTION LANGUAGES 48 1.9 CIRCUIT DESIGN 35 39 46 1.10 PHYSICAL DESIGN 49 52 CONTENTS .10.1 FLOORPLANNING 52 .10.2 STANDARD CELLS 55 .10.3 SNAP-TOGETHER CELLS .10.4 SLICE PLANS 59 .10.5 AREA ESTIMATION 59 55 1.11 DESIGN VERIFICATION 1.12 FABRICATION, PACKAGING, AND TESTING SUMMARY 63 EXERCISES 63 60 61 CHAPTER 2 MOS TRANSISTOR THEORY 2.1 INTRODUCTION 67 2.2 IDEAL I-V CHARACTERISTICS 71 2.3 C-V CHARACTERISTICS 75 2.3.1 SIMPLE MOS CAPACITANCE MODELS 75 FLT 2.3.2 DETAILED MOS GATE CAPACITANCE MODEL 77 0~ 2.3.3 DETAILED MOS DIFFUSION CAPACITANCE MODEL 80 2.4 NONIDEAL I-V EFFECTS 83 2.4.1 VELOCITY SATURATION AND MOBILITY DEGRADATION 84 2.4.2 CHANNEL LENGTH MODULATION 86 2.4.3 BODY EFFECT 87 2.4.4 SUBTHRESHOLD CONDUCTION 88 2.4.5 JUNCTION LEAKAGE 89 2.4.6 TUNNELING 90 2.4.7 TEMPERATURE DEPENDENCE 90 2.4.8 GEOMETRY DEPENDENCE 92 2.4.9 SUMMARY 92 2.5 DC TRANSFER CHARACTERISTICS 94 2.5.1 COMPLEMENTARY CMOS INVERTER DC CHARACTERISTICS 94 2.5.2 BETA RATIO EFFECTS 97 2.5.3 NOISE MARGIN 98 2.5.4 RATIOED INVERTER TRANSFER FUNCTION 100 2.5.5 PASS TRANSISTOR DC CHARACTERISTICS 101 2.5.6 TRISTATE INVERTER 102 2.6 SWITCH-LEVEL RC DELAY MODELS 103 SUMMARY 107 EXERCISES 108 CONTENTS CHAPTER 3 CMOS PROCESSING TECHNOLOGY 3.1 INTRODUCTION 113 3.2 CMOS TECHNOLOGIES 113 3.2.1 BACKGROUND 113 3.2.2 WAFER FORMATION 114 3.2.3 PHOTOLITHOGRAPHY 115 3.2.4 WELL AND CHANNEL FORMATION 117 3.2.5 SILICON DIOXIDE (SIO2) 118 3.2.6 ISOLATION 119 3.2.7 GATE OXIDE 120 3.2.8 GATE AND SOURCE/DRAIN FORMATION 121 3.2.9 CONTACTS AND METALLIZATION 124 3.2.10 PASSIVATION 124 3.2.11 METROLOGY 125 3.3 LAYOUT DESIGN RULES 125 3.3.1 DESIGN RULE BACKGROUND 126 3.3.2 SCRIBE LINE AND OTHER STRUCTURES 130 3.3.3 MOSIS SCALABLE CMOS DESIGN RULES 130 3.3.4 MICRON DESIGN RULES 134 3.4 CMOS PROCESS ENHANCEMENTS 136 3.4.1 TRANSISTORS 136 3.4.2 INTERCONNECT 140 3.4.3 CIRCUIT ELEMENTS 141 3.4.4 BEYOND CONVENTIONAL CMOS 148 3.5 TECHNOLOGY-RELATED CAD ISSUES 148 3.5.1 DESIGN RULE CHECKING (DRC) 149 3.5.2 CIRCUIT EXTRACTION 150 3.6 MANUFACTURING ISSUES 151 3.6.1 ANTENNA RULES 151 3.6.2 LAYER DENSITY RULES 152 3.6.3 RESOLUTION ENHANCEMENT RULES 153 3 7 ISN&NNS^RINERTPSFL!! 1 J»# ^^^^^^M^BJIUMHHMWHWIH ********** XJJ 3.8 HISTORICAL PERSPECTIVE 154 SUMMARY 154 EXERCISES 154 CHAPTER 4 CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION 4.1 INTRODUCTION 157 4.2 DELAY ESTIMATION 158 4.2.1 RC DELAY MODELS 159 4.2.2 LINEAR DELAY MODEL 165 4.2.3 LOGICA L EFFORT 166 4.2.4 PARASITIC DELAY 167 0~ 4.2.5 LIMITATIONS TO THE LINEAR DELAY MODEL 169 4.3 LOGICAL EFFORT AND TRANSISTOR SIZING 173 4.3.1 DELAY IN A LOGIC GATE 173 4.3.2 DELAY IN MULTISTAGE LOGIC NETWORKS 174 4.3.3 CHOOSING THE BEST NUMBER OF STAGES 178 4.3.4 EXAMPLE 181 4.3.5 SUMMARY AND OBSERVATIONS 183 $~ 4.3.6 LIMITATIONS OF LOGICAL EFFORT 185 W 4.3.7 EXTRACTING LOGICAL EFFORT FROM DATASHEETS 185 4.4 POWER DISSIPATION 186 4.4.1 STATIC DISSIPATION 188 4.4.2 DYNAMIC DISSIPATION 190 4.4.3 LOW-POWER DESIGN 191 4.5 INTERCONNECT 196 4.5.1 RESISTANCE 198 4.5.2 CAPACITANCE 200 4.5.3 DELAY 205 4.5.4 CROSSTALK 207 W 4.5.5 INDUCTANCE 210 F 4.5.6 TEMPERATURE DEPENDENCE 216 F 4.5. 7 AN ASIDE ON EFFECTIVE RESISTANCE AND ELMORE DELAY 216 4.6 WIRE ENGINEERING 219 4.6.1 WIDTH AND SPACING 219 4.6.2 LAYER SELECTION 219 4.6.3 SHIELDING 221 4.6.4 REPEATERS 221 4.6.5 IMPLICATIONS FOR LOGICAL EFFORT 227 #T 4.6.6 CROSSTALK CONTROL 227 $~ 4.6.7 LOW-SWING SIGNALING 229 4.7 DESIGN MARGIN 231 * 4.7.1 SUPPLY VOLTAGE 232 4.7.2 TEMPERATURE 232 4.7.3 PROCESS VARIATION 233 CONTENTS 4.7.4 DESIGN CORNERS 233 (T 4.7.5 MATCHING 235 0~ 4.7.6 DELAY TRACKING 237 4.8 RELIABILITY 239 4.8.1 RELIABILITY TERMINOLOGY 239 4.8.2 ELECTROMIGRATION 240 4.8.3 SELF-HEATING 241 4.8.4 HOT CARRIERS 241 4.8.5 LATCHUP 242 4.8.6 OVERVOLTAGE FAILURE 244 4.8.7 SOFT ERRORS 245 4.9 SCALING 245 4.9.1 TRANSISTOR SCALING 246 4.9.2 INTERCONNECT SCALING 249 4.9.3 INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 251 4.9.4 IMPACTS ON DESIGN 252 4.11 HISTORICAL PERSPECTIVE 259 SUMMARY 264 EXERCISES 266 CHAPTER 5 CIRCUIT SIMULATION 5.1 INTRODUCTION 273 5.2 A SPICETUTORIAL 274 5.2.1 SOURCES AND PASSIVE COMPONENTS 274 5.2.2 TRANSISTOR DC ANALYSIS 279 5.2.3 INVERTER TRANSIENT ANALYSIS 280 5.2.4 SUBCIRCUITS AND MEASUREMENT 281 5.2.5 OPTIMIZATION 284 5.2.6 OTHER HSPICE COMMANDS 286 5.3 DEVICE MODELS 287 5.3.1 LEVEL 1 MODELS 287 5.3.2 LEVEL 2 AND 3 MODELS 288 5.3.3 BSIM MODELS 288 5.3.4 DIFFUSION CAPACITANCE MODELS 289 5.3.5 DESIGN CORNERS 290 5.4 DEVICE CHARACTERIZATION 292 5.4.1 L-V CHARACTERISTICS 293 5.4.2 THRESHOLD VOLTAGE 293 5.4.3 GATE CAPACITANCE 296 CONTENTS 5.4.4 PARASITIC CAPACITANCE 299 5.4.5 EFFECTIVE RESISTANCE 299 5.4.6 COMPARISON OF PROCESSES 301 5.4.7 PROCESS AND ENVIRONMENTAL SENSITIVITY 303 5.5 CIRCUIT CHARACTERIZATION 303 5.5.1 PATH SIMULATIONS 305 5.5.2 DC TRANSFER CHARACTERISTICS 305 5.5.3 LOGICAL EFFORT 306 5.5.4 POWER AND ENERGY 309 5.5.5 SIMULATING MISMATCHES 310 5.5.6 MONTE CARLO SIMULATION 310 5.6 INTERCONNECT SIMULATION 311 5.7 MWUJJUJWIBBWI 315 SUMMARY 316 EXERCISES 317 CHAPTER 6 COMBINATIONAL CIRCUIT DESIGN 6.1 INTRODUCTION 319 6.2 CIRCUIT FAMILIES 320 6.2.1 STATIC CMOS 321 6.2.2 RATIOED CIRCUITS 327 6.2.3 CASCODE VOLTAGE SWITCH LOGIC 331 6.2.4 DYNAMIC CIRCUITS 332 6.2.5 PASS-TRANSISTOR CIRCUITS 345 6.3 CIRCUIT PITFALLS 350 6.3.1 THRESHOLD DROPS 351 6.3.2 RATIO FAILURES 352 6.3.3 LEAKAGE 352 6.3.4 CHARGE SHARING 353 6.3.5 POWER SUPPLY NOISE 353 6.3.6 HOT SPOTS 354 6.3.7 MINORITY CARRIER INJECTION 355 6.3.8 BACK-GATE COUPLING 356 6.3.9 DIFFUSION INPUT NOISE SENSITIVITY 357 6.3.10 PROCESS SENSITIVITY 357 6.3.1 1 QQQ\| DOMINO NOISE BUDGETS 357 6.4 MORE CIRCUIT FAMILIES 359 ,, 6.4.1 DIFFERENTIAL CIRCUITS 359 6.4.2 SENSE-AMPLIFIER CIRCUITS 360 CONTENTS 6.4.3 BICMOS CIRCUITS 365 6.4.4 OTHER CIRCUIT FAMILIES 365 6.5 LOW-POWER LOGIC DESIGN 366 6.6 COMPARISON OF CIRCUIT FAMILIES 367 6.7 SILICON-ON-INSULATOR CIRCUIT DESIGN 369 6.7.1 FLOATING BODY VOLTAGE 370 6.7.2 SOI ADVANTAGES 371 6.7.3 SOI DISADVANTAGES 372 6.7.4 IMPLICATIONS FOR CIRCUIT STYLES 373 6.7.5 SUMMARY 373 6.8 IGWUILMIJWFFLHHL 374 6.9 HISTORICAL PERSPECTIVE 375 SUMMARY 377 EXERCISES 378 CHAPTER 7 SEQUENTIAL CIRCUIT DESIGN 7.1 INTRODUCTION 383 7.2 SEQUENCING STATIC CIRCUITS 384 7.2.1 SEQUENCING METHODS 385 7.2.2 MAX-DELAY CONSTRAINTS 388 7.2.3 MIN-DELAY CONSTRAINTS 392 7.2.4 TIME BORROWING 396 7.2.5 CLOCK SKEW 399 7.3 CIRCUIT DESIGN OF LATCHES AND FLIP-FLOPS 402 7.3.1 CONVENTIONAL CMOS LATCHES 402 7.3.2 CONVENTIONAL CMOS FLIP-FLOPS 405 7.3.3 PULSED LATCHES 407 7.3.4 RESETTABLE LATCHES AND FLIP-FLOPS 408 7.3.5 ENABLED LATCHES AND FLIP-FLOPS 410 7.3.6 INCORPORATING LOGIC INTO LATCHES 410 7.3.7 KLASS SEMIDYNAMIC FLIP-FLOP (SDFF) 411 7.3.8 DIFFERENTIAL FLIP-FLOPS 412 (JF 7.3.9 TRUE SINGLE-PHASE-CLOCK (TSPC) LATCHES AND FLIP-FLOPS 414 7.4 STATIC SEQUENCING ELEMENT METHODOLOGY 414 7.4.1 CHOICE OF ELEMENTS 415 7.4.2 LOW-POWER SEQUENTIAL DESIGN 417 7.4.3 TWO-PHASE TIMING TYPES 418 7.4.4 ^CHARACTERIZING SEQUENCING ELEMENT DELAYS 422 CONTENTS 7.5 SEQUENCING DYNAMIC CIRCUITS 426 7.5.1 TRADITIONAL DOMINO CIRCUITS 427 7.5.2 SKEW-TOLERANT DOMINO CIRCUITS 428 7.5.3 UNFOOTED DOMINO GATE TIMING 438 7.5.4 NONMONOTONIC TECHNIQUES 441 7.5.5 STATIC-TO-DOMINO INTERFACE 449 7.5.6 DELAYED KEEPERS 453 7.6 SYNCHRONIZERS 453 7.6.1 METASTABILITY 454 7.6.2 A SIMPLE SYNCHRONIZER 458 7.6.3 COMMUNICATING BETWEEN ASYNCHRONOUS CLOCK DOMAINS 460 7.6.4 COMMON SYNCHRONIZER MISTAKES 461 7.6.5 ARBITERS 463 0~ 7.6.6 DEGREES OF SYNCHRONY 464 7.7 WAVE PIPELINING 464 7.8 MWUJMIMWHIG 467 7.9 CAS E STUDY: PENTIUM 4 AND ITANIUM 2 SEQUENCING METHODOLOGIES 468 7.9.1 PENTIUM 4 SEQUENCING 470 7.9.2 ITANIUM 2 SEQUENCING 470 SUMMARY 473 EXERCISES 475 CHAPTER 8 DESIGN METHODOLOGY AND TOOLS 8.1 INTRODUCTION 479 8.2 STRUCTURED DESIGN STRATEGIES 481 8.2.1 A SOFTWARE RADIOA SYSTEM EXAMPLE 482 8.2.2 HIERARCHY 485 8.2.3 REGULARITY 488 8.2.4 MODULARITY 492 8.2.5 LOCALITY 495 8.2.6 SUMMARY 498 8.3 DESIGN METHODS 498 8.3.1 MICROPROCESSOR/DSP 498 8.3.2 PROGRAMMABLE LOGIC 499 8.3.3 GATE ARRAY AND SEA OF GATES DESIGN 507 8.3.4 CELL-BASED DESIGN 509 ^8.3.5 FULL CUSTOM DESIGN 511 8.3.6 PLATFORM-BASED DESIGNSYSTEM ON A CHIP 518 8.3.7 SUMMARY 519 CONTENTS 8.4 DESIGN FLOWS 520 8.4.1 BEHAVIORAL SYNTHESIS DESIGN FLOW (ASIC DESIGN FLOW) 522 8.4.2 AUTOMATED LAYOUT GENERATION 528 8.4.3 MIXED-SIGNAL OR CUSTOM-DESIGN FLOW 532 8.4.4 PROGRAMMED BEHAVIORAL SYNTHESIS 535 8.5 DESIGN ECONOMICS 535 8.5.1 NON-RECURRING ENGINEERING COSTS (NRES) 537 8.5.2 RECURRING COSTS 539 8.5.3 FIXED COSTS 541 8.5.4 SCHEDULE 541 8.5.5 PERSONPOWER 542 8.5.6 PROJECT MANAGEMENT 544 8.5.7 DESIGN REUSE 544 8.6 DATA SHEETS AND DOCUMENTATION 545 8.6.1 THE SUMMARY 545 8.6.2 PINOUT 546 8.6.3 DESCRIPTION OF OPERATION 546 8.6.4 DC SPECIFICATIONS 546 8.6.5 AC SPECIFICATIONS 546 8.6.6 PACKAGE DIAGRAM 547 8.6.7 PRINCIPLES OF OPERATION MANUAL 547 I 8.6.8 USER MANUAL 547 I 0- 8.7 CLOSING THE GAP BETWEEN ASIC AND CUSTOM 547 T 8.7.1 MICROARCHITECTURE 548 I 8.7. 2 SEQUENCING OVERHEAD 548 I 8.7.3 CIRCUIT FAMILIES 549 I 8.7.4 LOGIC DESIGN 549 I 8.7.5 CELL AND WIRE DESIGN 550 I 8.7.6 LAYOUT 550 8.7.7 PROCESS VARIATION 550 8.7.8 SUMMARY 551 8.8 CMOS PHYSICAL DESIGN STYLES 551 8.8.1 STATIC CMOS GATE LAYOUT 551 8.8.2 GENERAL CMOS LAYOUT GUIDELINES 553 8.8.3 LAYOUT OPTIMIZATION FOR PERFORMANCE 556 8.9 INTERCHANGE FORMATS 558 8.9.1 GDS2 STREAM 558 8.9.2 CALTECH INTERMEDIATE FORMAT (CIF) 558 8.9.3 LIBRARY EXCHANGE FORMAT (LEF) 558 8.9.4 DESIGN EXCHANGE FORMAT (DEF) 559 8.9.5 STANDARD DELAY FORMAT (SDF) 560 8.9.6 DSPFANDSPEF 561 CONTENTS 8.9.7 ADVANCED LIBRARY FORMAT (ALF) 562 8.9.8 WAVES WAVEFORM AND VECTOR EXCHANGE SPECIFICATION 562 8.9.9 PHYSICAL DESIGN EXCHANGE FORMAT (PDEF) 563 8.9.10 OPENACCESS 563 8.10 HISTORICAL PERSPECTIVE 564 EXERCISES 565 CHAPTER 9 TESTING AND VERIFICATION 9.1 INTRODUCTION 567 9.1.1 LOGIC VERIFICATION 568 9.1.2 BASIC DIGITAL DEBUGGING HINTS 570 9.1.3 MANUFACTURING TESTS 573 9.2 TESTERS, TEST FIXTURES, AND TEST PROGRAMS 575 9.2.1 TESTERS AND TEST FIXTURES 575 9.2.2 TEST PROGRAMS 577 9.2.3 HANDLERS 579 9.3 LOGIC VERIFICATION PRINCIPLES 579 9.3.1 TEST BENCHES AND HARNESSES 579 9.3.2 REGRESSION TESTING 582 9.3.3 VERSION CONTROL 584 9.3.4 BUG TRACKING 584 9.4 SILICON DEBUG PRINCIPLES 584 9.5 MANUFACTURING TEST PRINCIPLES 588 9.5.1 FAULT MODELS 589 9.5.2 OBSERVABILITY 592 9.5.3 CONTROLLABILITY 592 9.5.4 FAULT COVERAGE 593 9.5.5 AUTOMATIC TEST PATTERN GENERATION (ATPG) 593 9.5.6 DELAY FAULT TESTING 594 9.6 DESIGN FOR TESTABILITY 594 9.6.1 AD HOC TESTING 595 9.6.2 SCAN DESIGN 596 9.6.3 BUILT-IN SELF-TEST (BIST) 602 9.6.4 IDDQTESTING 608 9.6.5 DESIGN FOR MANUFACTURABILITY 608 9.7 BOUNDARY SCAN 609 / 9.7.1 THE TEST ACCESS PORT (TAP) 611 9.7.2 THE TEST LOGIC ARCHITECTURE AND TEST ACCESS PORT 611 CONTENTS 9.7.3 THE TAP CONTROLLER 612 9.7.4 THE INSTRUCTION REGISTER 614 9.7.5 TEST DATA REGISTERS 616 9.7.6 SUMMARY 620 9.8 SYSTEM-ON-CHIP (SOC) TESTING 622 9.9 MIXED-SIGNAL TESTING 625 9.10 RELIABILITY TESTING 626 9.11 TESTING IN A UNIVERSITY ENVIRONMENT 627 9.12 IIIU^IL-IATF.IANJHGA 629 SUMMARY 635 EXERCISES 636 LJ DATAPATH SUBSYSTEMS 10.1 INTRODUCTION 637 10.2 ADDITION/SUBTRACTION 638 10.2.1 SINGLE-BIT ADDITION 638 10.2.2 CARRY-PROPAGATE ADDITION 645 10.2.3 ADDER VARIANTS 677 10.3 ONE/ZERO DETECTORS 679 10.4 COMPARATORS 681 10.4.1 MAGNITUDE COMPARATOR 681 10.4.2 EQUALITY COMPARATOR 681 10.4.3 K = J+B COMPARATOR 682 10.5 COUNTERS 683 10.5.1 BINARY COUNTERS 683 10.5.2 LINEAR-FEEDBACK SHIFT REGISTERS 684 10.6 BOOLEAN LOGICAL OPERATIONS 686 10.7 CODING 686 10.7.1 PARITY 687 10.7.2 ERROR-CORRECTING CODES 687 10.7.3 GRAY CODES 688 10.7.4 XOR/XNOR CIRCUIT FORMS 689 10.8 SHIFTERS 691 10.9 MULTIPLICATION 693 10.9.1 UNSIGNED ARRAY MULTIPLICATION 694 10.9.2 2 S COMPLEMENT ARRAY MULTIPLICATION 696 0- 10.9.3 -BOOTH ENCODING 698 CONTENTS 0 10.9.4 WALLACE TREE MULTIPLICATION 703 0 10.9.5 HYBRID MULTIPLICATION 705 0 10.9.6 FUSED MULTIPLY-ADD 705 0 10.9.7 SERIAL MULTIPLICATION 705 10.10 PARALLEL-PREFIX COMPUTATIONS 706 IO.IL IJJUIMMIJJNUSTGI 708 10.12 HISTORICAL PERSPECTIVE 709 SUMMARY 709 EXERCISES 710 CHAPTER 11 ARRAY SUBSYSTEMS 11.1 INTRODUCTION 713 11.2 SRAM 715 11.2.1 MEMORY CELL READ/WRITE OPERATION 718 11.2.2 DECODERS 719 11.2.3 BITLINE CONDITIONING AND COLUMN CIRCUITRY 725 0~ 11.2.4 MULTI-PORTED SRAM AND REGISTER FILES 728 0 11.2. 5 LARGE SRAMS 730 IFF 11.2.6 LOGICAL EFFORT OF RAMS AND REGISTER FILES 731 0 11.2.7 CASE STUDY: ITANIUM 2 CACHE 733 11.3 DRAM 734 0~ 11.3.1 SUBARRAY ARCHITECTURES 735 0 11.3.2 COLUMN CIRCUITRY 738 IFF 11.3.3 APPLICATIONS TO CMOS SYSTEMS-ON-CHIP 738 11.4 READ-ONLY MEMORY 739 0 11.4.1 PROGRAMMABLE ROMS 741 0 11.4.2 NANDROMS 743 11.5 SERIAL ACCESS MEMORIES 744 11.5.1 SHIFT REGISTERS 745 11.5.2 QUEUES (FIFO, LIFO) 746 11.6 CONTENT-ADDRESSABLE MEMORY , 747 11.7 PROGRAMMABLE LOGIC ARRAYS 750 11.8 ARRAY YIELD, RELIABILITY, AND SELF-TEST 756 11.9 HISTORICAL PERSPECTIVE 757 SUMMARY 759 EXERCISES 760 CONTENTS CHAPTER 12 SPECIAL-PURPOSE SUBSYSTEMS 12.1 INTRODUCTION 761 12.2 PACKAGING 761 12.2.1 PACKAGE OPTIONS 762 1 2.2.2 CHIP-TO-PACKAGE CONNECTIONS 764 1 2.2.3 PACKAGE PARASITICS 765 1 2.2.4 HEAT DISSIPATION 765 12.3 POWER DISTRIBUTION 767 12.3.1 ON-CHIP POWER DISTRIBUTION NETWORK 768 12.3.2 IR DROPS 771 12.3.3 LDI/DT NOISE 772 1 2.3.4 ON-CHIP BYPASS CAPACITANCE 773 0 12.3.5 POWER NETWORK MODELING 775 0 12.3.6 SIGNAL RETURN PATHS 778 0 12.3.7 POWER SUPPLY FILTERING 779 0 12.3.8 SUBSTRATE NOISE 780 12.4 I/O 780 12.4.1 BASIC I/O PAD CIRCUITS 781 12.4.2 L^^JG MOSIS I/O PADS 784 0 12.4.3 LEVEL CONVERTERS 784 12.5 CLOCK 786 12.5.1 DEFINITIONS 786 12.5.2 CLOCK SYSTEM ARCHITECTURE 789 12.5.3 GLOBAL CLOCK GENERATION 790 12.5.4 GLOBAL CLOCK DISTRIBUTION 793 12.5.5 LOCAL CLOCK GATERS 798 0~ 12.5.6 CLOCK SKEW BUDGETS 800 0 1 2.5.7 ADAPTIVE DESKEWING 806 IFF 12.5.8 CLOCKING ALTERNATIVES 807 12.6 ANALOG CIRCUITS 808 12.6.1 MOS SMALL-SIGNAL MODEL 808 12.6.2 COMMON SOURCE AMPLIFIER 811 12.6.3 THE CMOS INVERTER AS AN AMPLIFIER 812 1 2.6.4 CURRENT MIRRORS 814 12.6.5 DIFFERENTIAL PAIRS 816 12.6.6 SIMPLE CMOS OPERATIONAL AMPLIFIER 819 1 2.6.7 DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERTER BASICS 819 1 2.6.8 DIGITAL-TO-ANALOG CONVERTERS 824 1 2.6.9 ANALOG-TO-DIGITAL CONVERTERS 828 12.6.10 RADIO FREQUENCY (RF) CIRCUITS 837 12.6.11 ANALOG SUMMARY 841 CONTENTS 12.8 HISTORICAL PERSPECTIVE 843 SUMMARY 845 EXERCISES 845 APPENDIX A VERILOG A.1 INTRODUCTION 849 A.2 BEHAVIORAL MODELING WITH CONTINUOUS ASSIGNMENTS 850 A.2.1 BITWISE OPERATORS 850 A.2.2 COMMENTS AND WHITE SPACE 851 A.2.3 REDUCTION OPERATORS 851 A.2.4 OTHE R OPERATORS 852 A.3 BASIC CONSTRUCTS 852 A.3.1 INTERNAL SIGNALS 852 A.3.2 PRECEDENCE 853 A.3.3 CONSTANTS 854 A.3.4 HIERARCHY 854 A.3.5 TRISTATES 855 A.3.6 BIT SWIZZLING 855 A.3.7 DELAYS 857 A.4 BEHAVIORAL MODELING WITH ALWAYS BLOCKS 857 A.4.1 REGISTERS 857 A.4.2 LATCHES 859 A.4.3 COUNTERS 859 A.4.4 COMBINATIONAL LOGIC 860 A.4.5 MEMORIES 866 A.4.6 BLOCKING AND NONBLOCKING ASSIGNMENT 867 A.5 FINITE STATE MACHINES 868 A.6 PARAMETERIZED MODULES 874 A.7 STRUCTURAL PRIMITIVES 874 A.8 TEST BENCHES , 875 A.9 PITFALLS 877 A.9.1 VERILOG STYLE GUIDELINES 877 A.9.2 INCORRECT STIMULUS LIST 878 A.9.3 MISSING BEGIN/END BLOCK 880 A.9.4 UNDEFINED OUTPUTS 880 A.9.5 INCOMPLET E SPECIFICATION OF CASES 882 CONTENTS APPENDIX B A.9.6 SHORTED OUTPUTS 884 A.9.7 INCORRECT USE OF NONBLOCKING ASSIGNMENTS 885 A.10 IGGILBBIL^ MIPS PROCESSOR 886 WHDL B.I INTRODUCTION 895 B.2 BEHAVIORAL MODELING WITH CONCURRENT SIGNAL ASSIGNMENTS 896 B.2.1 BITWISE OPERATORS 896 B.2.2 COMMENTS AND WHITE SPACE 897 B.2.3 OTHER OPERATORS 897 B.2.4 CONDITIONAL SIGNAL ASSIGNMENT STATEMENTS 898 B.2.5 SELECTED SIGNAL ASSIGNMENT STATEMENTS 898 B.3 BASIC CONSTRUCTS 899 B.3.1 BLOCKS, ENTITIES, AND ARCHITECTURES 899 B.3.2 INTERNAL SIGNALS 900 B.3.3 PRECEDENCE 900 B.3.4 HIERARCHY 901 B.3.5 BIT SWIZZLING 901 B.3.6 TYPES 902 B.3.7 LIBRARY AND USE CLAUSES 904 B.3.8 TRISTATES 905 B.3.9 DELAYS 906 B.4 BEHAVIORAL MODELING WITH PROCESS STATEMENTS 906 B.4.1 FLIP-FLOPS 906 B.4.2 LATCHES 908 B.4.3 COUNTERS 908 B.4.4 COMBINATIONAL LOGIC 909 B.4.5 MEMORIES 912 B.5 FINITE STATE MACHINES 913 B.6 PARAMETERIZED BLOCKS 915 B.7 LIUAIWIHU MIPS PROCESSOR 917 REFERENCES 927 INDEX 953
any_adam_object	1
author	Weste, Neil H. E. Harris, David Money 19XX-
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discipline	Informatik Elektrotechnik / Elektronik / Nachrichtentechnik
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id	DE-604.BV019774690
illustrated	Illustrated
indexdate	2024-12-20T12:05:35Z
institution	BVB
isbn	0321149017 0321269772
language	English
lccn	2004007092
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-013100770
oclc_num	54826075
open_access_boolean
owner	DE-91 DE-BY-TUM DE-898 DE-BY-UBR DE-Aug4 DE-526 DE-634 DE-859 DE-29T DE-11
owner_facet	DE-91 DE-BY-TUM DE-898 DE-BY-UBR DE-Aug4 DE-526 DE-634 DE-859 DE-29T DE-11
physical	XXIV, 967 S. Ill., graph. Darst. 24 cm
publishDate	2005
publishDateSearch	2005
publishDateSort	2005
publisher	Pearson/Addison-Wesley
record_format	marc
spellingShingle	Weste, Neil H. E. Harris, David Money 19XX- CMOS VLSI design a circuits and systems perspective aIntegrated circuits xVery large scale integration xdesign and construction aMetal oxide semiconductors, Complementary CMOS-Schaltung (DE-588)4148111-2 gnd VLSI (DE-588)4117388-0 gnd
subject_GND	(DE-588)4148111-2 (DE-588)4117388-0
title	CMOS VLSI design a circuits and systems perspective
title_auth	CMOS VLSI design a circuits and systems perspective
title_exact_search	CMOS VLSI design a circuits and systems perspective
title_full	CMOS VLSI design a circuits and systems perspective Neil H.E. Weste, David Harris
title_fullStr	CMOS VLSI design a circuits and systems perspective Neil H.E. Weste, David Harris
title_full_unstemmed	CMOS VLSI design a circuits and systems perspective Neil H.E. Weste, David Harris
title_short	CMOS VLSI design
title_sort	cmos vlsi design a circuits and systems perspective
title_sub	a circuits and systems perspective
topic	aIntegrated circuits xVery large scale integration xdesign and construction aMetal oxide semiconductors, Complementary CMOS-Schaltung (DE-588)4148111-2 gnd VLSI (DE-588)4117388-0 gnd
topic_facet	aIntegrated circuits xVery large scale integration xdesign and construction aMetal oxide semiconductors, Complementary CMOS-Schaltung VLSI
url	http://www.loc.gov/catdir/toc/ecip0416/2004007092.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013100770&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT westeneilhe cmosvlsidesignacircuitsandsystemsperspective AT harrisdavidmoney cmosvlsidesignacircuitsandsystemsperspective

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