Logical effort: designing fast CMOS circuits
Gespeichert in:
| Beteiligte Personen: | , , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
San Francisco, Calif.
Morgan Kaufmann Publishers
1999
|
| Schlagwörter: | |
| Links: | http://www.loc.gov/catdir/description/els033/98053860.html http://www.loc.gov/catdir/toc/els032/98053860.html |
| Umfang: | XV, 239 S. Ill. |
| ISBN: | 1558605576 |
Internformat
MARC
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| 100 | 1 | |a Sutherland, Ivan E. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Logical effort |b designing fast CMOS circuits |c Ivan Sutherland ; Robert Sproull ; David Harris |
| 264 | 1 | |a San Francisco, Calif. |b Morgan Kaufmann Publishers |c 1999 | |
| 300 | |a XV, 239 S. |b Ill. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 7 | |a CMOS (Circuit intégré) |2 rasuqam | |
| 650 | 4 | |a Logic devices | |
| 650 | 4 | |a Metal oxide semiconductors, Complementary | |
| 650 | 7 | |a Structure logique |2 rasuqam | |
| 650 | 4 | |a Delay faults (Semiconductors) | |
| 650 | 4 | |a Logic design | |
| 650 | 4 | |a Metal oxide semiconductors, Complementary |x Design and construction | |
| 650 | 0 | 7 | |a CMOS-Schaltung |0 (DE-588)4148111-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a CMOS-Schaltung |0 (DE-588)4148111-2 |D s |
| 689 | 0 | 1 | |a Logischer Entwurf |0 (DE-588)4168051-0 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 700 | 1 | |a Sproull, Robert F. |e Verfasser |4 aut | |
| 700 | 1 | |a Harris, David Money |d 19XX- |e Verfasser |0 (DE-588)173938035 |4 aut | |
| 856 | 4 | |u http://www.loc.gov/catdir/description/els033/98053860.html |3 Publisher description | |
| 856 | 4 | |u http://www.loc.gov/catdir/toc/els032/98053860.html |3 Table of contents | |
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-010456194 | |
Datensatz im Suchindex
| _version_ | 1818957957636816896 |
|---|---|
| any_adam_object | |
| author | Sutherland, Ivan E. Sproull, Robert F. Harris, David Money 19XX- |
| author_GND | (DE-588)173938035 |
| author_facet | Sutherland, Ivan E. Sproull, Robert F. Harris, David Money 19XX- |
| author_role | aut aut aut |
| author_sort | Sutherland, Ivan E. |
| author_variant | i e s ie ies r f s rf rfs d m h dm dmh |
| building | Verbundindex |
| bvnumber | BV017345283 |
| callnumber-first | T - Technology |
| callnumber-label | TK7871 |
| callnumber-raw | TK7871.99.M44 |
| callnumber-search | TK7871.99.M44 |
| callnumber-sort | TK 47871.99 M44 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4960 |
| ctrlnum | (OCoLC)40534543 (DE-599)BVBBV017345283 |
| dewey-full | 621.3815/2 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815/2 |
| dewey-search | 621.3815/2 |
| dewey-sort | 3621.3815 12 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV017345283 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T11:18:06Z |
| institution | BVB |
| isbn | 1558605576 |
| language | English |
| lccn | 98053860 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-010456194 |
| oclc_num | 40534543 |
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| owner | DE-898 DE-BY-UBR |
| owner_facet | DE-898 DE-BY-UBR |
| physical | XV, 239 S. Ill. |
| publishDate | 1999 |
| publishDateSearch | 1999 |
| publishDateSort | 1999 |
| publisher | Morgan Kaufmann Publishers |
| record_format | marc |
| spelling | Sutherland, Ivan E. Verfasser aut Logical effort designing fast CMOS circuits Ivan Sutherland ; Robert Sproull ; David Harris San Francisco, Calif. Morgan Kaufmann Publishers 1999 XV, 239 S. Ill. txt rdacontent n rdamedia nc rdacarrier CMOS (Circuit intégré) rasuqam Logic devices Metal oxide semiconductors, Complementary Structure logique rasuqam Delay faults (Semiconductors) Logic design Metal oxide semiconductors, Complementary Design and construction CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf CMOS-Schaltung (DE-588)4148111-2 s Logischer Entwurf (DE-588)4168051-0 s 1\p DE-604 Sproull, Robert F. Verfasser aut Harris, David Money 19XX- Verfasser (DE-588)173938035 aut http://www.loc.gov/catdir/description/els033/98053860.html Publisher description http://www.loc.gov/catdir/toc/els032/98053860.html Table of contents 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Sutherland, Ivan E. Sproull, Robert F. Harris, David Money 19XX- Logical effort designing fast CMOS circuits CMOS (Circuit intégré) rasuqam Logic devices Metal oxide semiconductors, Complementary Structure logique rasuqam Delay faults (Semiconductors) Logic design Metal oxide semiconductors, Complementary Design and construction CMOS-Schaltung (DE-588)4148111-2 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
| subject_GND | (DE-588)4148111-2 (DE-588)4168051-0 |
| title | Logical effort designing fast CMOS circuits |
| title_auth | Logical effort designing fast CMOS circuits |
| title_exact_search | Logical effort designing fast CMOS circuits |
| title_full | Logical effort designing fast CMOS circuits Ivan Sutherland ; Robert Sproull ; David Harris |
| title_fullStr | Logical effort designing fast CMOS circuits Ivan Sutherland ; Robert Sproull ; David Harris |
| title_full_unstemmed | Logical effort designing fast CMOS circuits Ivan Sutherland ; Robert Sproull ; David Harris |
| title_short | Logical effort |
| title_sort | logical effort designing fast cmos circuits |
| title_sub | designing fast CMOS circuits |
| topic | CMOS (Circuit intégré) rasuqam Logic devices Metal oxide semiconductors, Complementary Structure logique rasuqam Delay faults (Semiconductors) Logic design Metal oxide semiconductors, Complementary Design and construction CMOS-Schaltung (DE-588)4148111-2 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
| topic_facet | CMOS (Circuit intégré) Logic devices Metal oxide semiconductors, Complementary Structure logique Delay faults (Semiconductors) Logic design Metal oxide semiconductors, Complementary Design and construction CMOS-Schaltung Logischer Entwurf |
| url | http://www.loc.gov/catdir/description/els033/98053860.html http://www.loc.gov/catdir/toc/els032/98053860.html |
| work_keys_str_mv | AT sutherlandivane logicaleffortdesigningfastcmoscircuits AT sproullrobertf logicaleffortdesigningfastcmoscircuits AT harrisdavidmoney logicaleffortdesigningfastcmoscircuits |