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Logic synthesis and verification algorithms:

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Bibliographic Details
Main Authors:	Hachtel, Gary D. (Author), Somenzi, Fabio (Author)
Format:	Book
Language:	English
Published:	Boston [u.a.] Kluwer 2000
Edition:	3. print.
Subjects:	Logiksynthese Logischer Entwurf
Physical Description:	XXXII, 564 S. graph. Darst.
ISBN:	0792397460

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MARC


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Record in the Search Index

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discipline	Elektrotechnik / Elektronik / Nachrichtentechnik
edition	3. print.
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id	DE-604.BV014657176
illustrated	Illustrated
indexdate	2024-12-20T11:06:13Z
institution	BVB
isbn	0792397460
language	English
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oclc_num	250040542
open_access_boolean
owner	DE-20
owner_facet	DE-20
physical	XXXII, 564 S. graph. Darst.
publishDate	2000
publishDateSearch	2000
publishDateSort	2000
publisher	Kluwer
record_format	marc
spelling	Hachtel, Gary D. Verfasser aut Logic synthesis and verification algorithms by Gary D. Hachtel ; Fabio Somenzi 3. print. Boston [u.a.] Kluwer 2000 XXXII, 564 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Logiksynthese (DE-588)4348178-4 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 s DE-604 Logiksynthese (DE-588)4348178-4 s Somenzi, Fabio Verfasser aut
spellingShingle	Hachtel, Gary D. Somenzi, Fabio Logic synthesis and verification algorithms Logiksynthese (DE-588)4348178-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd
subject_GND	(DE-588)4348178-4 (DE-588)4168051-0
title	Logic synthesis and verification algorithms
title_auth	Logic synthesis and verification algorithms
title_exact_search	Logic synthesis and verification algorithms
title_full	Logic synthesis and verification algorithms by Gary D. Hachtel ; Fabio Somenzi
title_fullStr	Logic synthesis and verification algorithms by Gary D. Hachtel ; Fabio Somenzi
title_full_unstemmed	Logic synthesis and verification algorithms by Gary D. Hachtel ; Fabio Somenzi
title_short	Logic synthesis and verification algorithms
title_sort	logic synthesis and verification algorithms
topic	Logiksynthese (DE-588)4348178-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd
topic_facet	Logiksynthese Logischer Entwurf
work_keys_str_mv	AT hachtelgaryd logicsynthesisandverificationalgorithms AT somenzifabio logicsynthesisandverificationalgorithms

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