Logic synthesis and verification algorithms:
Gespeichert in:
| Beteiligte Personen: | , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Boston [u.a.]
Kluwer
2000
|
| Ausgabe: | 3. print. |
| Schlagwörter: | |
| Umfang: | XXXII, 564 S. graph. Darst. |
| ISBN: | 0792397460 |
Internformat
MARC
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| 245 | 1 | 0 | |a Logic synthesis and verification algorithms |c by Gary D. Hachtel ; Fabio Somenzi |
| 250 | |a 3. print. | ||
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Datensatz im Suchindex
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|---|---|
| any_adam_object | |
| author | Hachtel, Gary D. Somenzi, Fabio |
| author_facet | Hachtel, Gary D. Somenzi, Fabio |
| author_role | aut aut |
| author_sort | Hachtel, Gary D. |
| author_variant | g d h gd gdh f s fs |
| building | Verbundindex |
| bvnumber | BV014657176 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
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| callnumber-subject | TK - Electrical and Nuclear Engineering |
| ctrlnum | (OCoLC)250040542 (DE-599)BVBBV014657176 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 3. print. |
| format | Book |
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| id | DE-604.BV014657176 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T11:06:13Z |
| institution | BVB |
| isbn | 0792397460 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009948995 |
| oclc_num | 250040542 |
| open_access_boolean | |
| owner | DE-20 |
| owner_facet | DE-20 |
| physical | XXXII, 564 S. graph. Darst. |
| publishDate | 2000 |
| publishDateSearch | 2000 |
| publishDateSort | 2000 |
| publisher | Kluwer |
| record_format | marc |
| spelling | Hachtel, Gary D. Verfasser aut Logic synthesis and verification algorithms by Gary D. Hachtel ; Fabio Somenzi 3. print. Boston [u.a.] Kluwer 2000 XXXII, 564 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Logiksynthese (DE-588)4348178-4 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 s DE-604 Logiksynthese (DE-588)4348178-4 s Somenzi, Fabio Verfasser aut |
| spellingShingle | Hachtel, Gary D. Somenzi, Fabio Logic synthesis and verification algorithms Logiksynthese (DE-588)4348178-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
| subject_GND | (DE-588)4348178-4 (DE-588)4168051-0 |
| title | Logic synthesis and verification algorithms |
| title_auth | Logic synthesis and verification algorithms |
| title_exact_search | Logic synthesis and verification algorithms |
| title_full | Logic synthesis and verification algorithms by Gary D. Hachtel ; Fabio Somenzi |
| title_fullStr | Logic synthesis and verification algorithms by Gary D. Hachtel ; Fabio Somenzi |
| title_full_unstemmed | Logic synthesis and verification algorithms by Gary D. Hachtel ; Fabio Somenzi |
| title_short | Logic synthesis and verification algorithms |
| title_sort | logic synthesis and verification algorithms |
| topic | Logiksynthese (DE-588)4348178-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
| topic_facet | Logiksynthese Logischer Entwurf |
| work_keys_str_mv | AT hachtelgaryd logicsynthesisandverificationalgorithms AT somenzifabio logicsynthesisandverificationalgorithms |