Test pattern generation and verification for logic circuits: an implication graph based approach
Gespeichert in:
| Beteilige Person: | |
|---|---|
| Format: | Hochschulschrift/Dissertation Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
München
Hieronymus
2001
|
| Ausgabe: | Als Typoskript gedr. |
| Schriftenreihe: | Informationstechnik
|
| Schlagwörter: | |
| Umfang: | III, 190, XXVI S. Ill., graph. Darst. |
| ISBN: | 3897911922 |
Internformat
MARC
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| 245 | 1 | 0 | |a Test pattern generation and verification for logic circuits |b an implication graph based approach |c Paul Tafertshofer |
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Datensatz im Suchindex
| DE-BY-TUM_call_number | 0001 DM 21585 |
|---|---|
| DE-BY-TUM_katkey | 1213449 |
| DE-BY-TUM_location | Mag |
| DE-BY-TUM_media_number | 040006015336 |
| _version_ | 1821932491025416194 |
| any_adam_object | |
| author | Tafertshofer, Paul |
| author_facet | Tafertshofer, Paul |
| author_role | aut |
| author_sort | Tafertshofer, Paul |
| author_variant | p t pt |
| building | Verbundindex |
| bvnumber | BV013837637 |
| classification_tum | ELT 359d ELT 273d |
| ctrlnum | (OCoLC)76274408 (DE-599)BVBBV013837637 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Als Typoskript gedr. |
| format | Thesis Book |
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| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV013837637 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T10:54:26Z |
| institution | BVB |
| isbn | 3897911922 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-009464654 |
| oclc_num | 76274408 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-12 DE-703 DE-634 |
| owner_facet | DE-91 DE-BY-TUM DE-12 DE-703 DE-634 |
| physical | III, 190, XXVI S. Ill., graph. Darst. |
| publishDate | 2001 |
| publishDateSearch | 2001 |
| publishDateSort | 2001 |
| publisher | Hieronymus |
| record_format | marc |
| series2 | Informationstechnik |
| spellingShingle | Tafertshofer, Paul Test pattern generation and verification for logic circuits an implication graph based approach Digitale integrierte Schaltung (DE-588)4113313-4 gnd Selbsttest (DE-588)4054433-3 gnd Fehlererkennung (DE-588)4133764-5 gnd Algorithmus (DE-588)4001183-5 gnd Testmustergenerierung (DE-588)4234817-1 gnd |
| subject_GND | (DE-588)4113313-4 (DE-588)4054433-3 (DE-588)4133764-5 (DE-588)4001183-5 (DE-588)4234817-1 (DE-588)4113937-9 |
| title | Test pattern generation and verification for logic circuits an implication graph based approach |
| title_auth | Test pattern generation and verification for logic circuits an implication graph based approach |
| title_exact_search | Test pattern generation and verification for logic circuits an implication graph based approach |
| title_full | Test pattern generation and verification for logic circuits an implication graph based approach Paul Tafertshofer |
| title_fullStr | Test pattern generation and verification for logic circuits an implication graph based approach Paul Tafertshofer |
| title_full_unstemmed | Test pattern generation and verification for logic circuits an implication graph based approach Paul Tafertshofer |
| title_short | Test pattern generation and verification for logic circuits |
| title_sort | test pattern generation and verification for logic circuits an implication graph based approach |
| title_sub | an implication graph based approach |
| topic | Digitale integrierte Schaltung (DE-588)4113313-4 gnd Selbsttest (DE-588)4054433-3 gnd Fehlererkennung (DE-588)4133764-5 gnd Algorithmus (DE-588)4001183-5 gnd Testmustergenerierung (DE-588)4234817-1 gnd |
| topic_facet | Digitale integrierte Schaltung Selbsttest Fehlererkennung Algorithmus Testmustergenerierung Hochschulschrift |
| work_keys_str_mv | AT tafertshoferpaul testpatterngenerationandverificationforlogiccircuitsanimplicationgraphbasedapproach |
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