HDL chip design: a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog
Gespeichert in:
| Beteilige Person: | |
|---|---|
| Format: | Buch |
| Sprache: | Nichtbestimmte Sprache |
| Veröffentlicht: |
Madison, AL
Doone
1997
|
| Ausgabe: | 3. print., minor rev. |
| Schlagwörter: | |
| Umfang: | XVI, 448 S. graph. Darst. |
| ISBN: | 0965193438 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV011777983 | ||
| 003 | DE-604 | ||
| 005 | 19980318 | ||
| 007 | t| | ||
| 008 | 980216s1997 xx d||| |||| 00||| und d | ||
| 020 | |a 0965193438 |9 0-9651934-3-8 | ||
| 035 | |a (OCoLC)634257967 | ||
| 035 | |a (DE-599)BVBBV011777983 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | |a und | ||
| 049 | |a DE-91G | ||
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 084 | |a DAT 190f |2 stub | ||
| 100 | 1 | |a Smith, Douglas J. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a HDL chip design |b a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |c Douglas J. Smith |
| 250 | |a 3. print., minor rev. | ||
| 264 | 1 | |a Madison, AL |b Doone |c 1997 | |
| 300 | |a XVI, 448 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Hardwarebeschreibungssprache |0 (DE-588)4159102-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |D s |
| 689 | 2 | |8 1\p |5 DE-604 | |
| 689 | 3 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 3 | |8 2\p |5 DE-604 | |
| 689 | 4 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 4 | |8 3\p |5 DE-604 | |
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007948759 | |
Datensatz im Suchindex
| DE-BY-TUM_call_number | 0102 DAT 190f 2001 B 2494 |
|---|---|
| DE-BY-TUM_katkey | 901794 |
| DE-BY-TUM_location | 01 |
| DE-BY-TUM_media_number | 040020213972 |
| _version_ | 1821931581158195202 |
| any_adam_object | |
| author | Smith, Douglas J. |
| author_facet | Smith, Douglas J. |
| author_role | aut |
| author_sort | Smith, Douglas J. |
| author_variant | d j s dj djs |
| building | Verbundindex |
| bvnumber | BV011777983 |
| classification_rvk | ST 250 |
| classification_tum | DAT 190f |
| ctrlnum | (OCoLC)634257967 (DE-599)BVBBV011777983 |
| discipline | Informatik |
| edition | 3. print., minor rev. |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01929nam a2200505 c 4500</leader><controlfield tag="001">BV011777983</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">19980318 </controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">980216s1997 xx d||| |||| 00||| und d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0965193438</subfield><subfield code="9">0-9651934-3-8</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)634257967</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV011777983</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">und</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 250</subfield><subfield code="0">(DE-625)143626:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 190f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Smith, Douglas J.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">HDL chip design</subfield><subfield code="b">a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog</subfield><subfield code="c">Douglas J. Smith</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">3. print., minor rev.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Madison, AL</subfield><subfield code="b">Doone</subfield><subfield code="c">1997</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XVI, 448 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Kundenspezifische Schaltung</subfield><subfield code="0">(DE-588)4122250-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Hardwarebeschreibungssprache</subfield><subfield code="0">(DE-588)4159102-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Hardwarebeschreibungssprache</subfield><subfield code="0">(DE-588)4159102-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Kundenspezifische Schaltung</subfield><subfield code="0">(DE-588)4122250-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="3" ind2="0"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="4" ind2="0"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="4" ind2=" "><subfield code="8">3\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">3\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007948759</subfield></datafield></record></collection> |
| id | DE-604.BV011777983 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T10:18:28Z |
| institution | BVB |
| isbn | 0965193438 |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007948759 |
| oclc_num | 634257967 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | XVI, 448 S. graph. Darst. |
| publishDate | 1997 |
| publishDateSearch | 1997 |
| publishDateSort | 1997 |
| publisher | Doone |
| record_format | marc |
| spellingShingle | Smith, Douglas J. HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Kundenspezifische Schaltung (DE-588)4122250-7 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd Field programmable gate array (DE-588)4347749-5 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4122250-7 (DE-588)4159102-1 (DE-588)4347749-5 (DE-588)4268385-3 (DE-588)4254792-1 |
| title | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_auth | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_exact_search | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| title_full | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith |
| title_fullStr | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith |
| title_full_unstemmed | HDL chip design a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog Douglas J. Smith |
| title_short | HDL chip design |
| title_sort | hdl chip design a practical guide for designing synthesizing and simulating asics and fpgas using vhdl or verilog |
| title_sub | a practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog |
| topic | Kundenspezifische Schaltung (DE-588)4122250-7 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd Field programmable gate array (DE-588)4347749-5 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| topic_facet | Kundenspezifische Schaltung Hardwarebeschreibungssprache Field programmable gate array VERILOG VHDL |
| work_keys_str_mv | AT smithdouglasj hdlchipdesignapracticalguidefordesigningsynthesizingandsimulatingasicsandfpgasusingvhdlorverilog |
Paper/Kapitel scannen lassen
Teilbibliothek Mathematik & Informatik
| Signatur: |
0102 DAT 190f 2001 B 2494
Lageplan |
|---|---|
| Exemplar 1 | Ausleihbar Am Standort |