Partitioning VLSI circuits for parallel simulation on transistor level:
Gespeichert in:
| Beteiligte Personen: | , , |
|---|---|
| Format: | Buch |
| Sprache: | Nichtbestimmte Sprache |
| Veröffentlicht: |
München
1997
|
| Schriftenreihe: | Sonderforschungsbereich Methoden und Werkzeuge für die Nutzung Paralleler Rechnerarchitekturen <München>: [SFB-Bericht / A]
1997,9 |
| Umfang: | 18 S. Ill. |
Internformat
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| 100 | 1 | |a Fröhlich, Norbert |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Partitioning VLSI circuits for parallel simulation on transistor level |c Norbert Fröhlich ; Rolf Schlagenhaft ; Josef Fleischmann |
| 264 | 1 | |a München |c 1997 | |
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| 700 | 1 | |a Schlagenhaft, Rolf |e Verfasser |4 aut | |
| 700 | 1 | |a Fleischmann, Josef |e Verfasser |4 aut | |
| 810 | 2 | |a A] |t Sonderforschungsbereich Methoden und Werkzeuge für die Nutzung Paralleler Rechnerarchitekturen <München>: [SFB-Bericht |v 1997,9 |w (DE-604)BV004627888 |9 1997,9 | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007938989 | |
Datensatz im Suchindex
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| id | DE-604.BV011765201 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T10:18:15Z |
| institution | BVB |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007938989 |
| oclc_num | 634133621 |
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| physical | 18 S. Ill. |
| publishDate | 1997 |
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| series2 | Sonderforschungsbereich Methoden und Werkzeuge für die Nutzung Paralleler Rechnerarchitekturen <München>: [SFB-Bericht / A] |
| spellingShingle | Fröhlich, Norbert Schlagenhaft, Rolf Fleischmann, Josef Partitioning VLSI circuits for parallel simulation on transistor level |
| title | Partitioning VLSI circuits for parallel simulation on transistor level |
| title_auth | Partitioning VLSI circuits for parallel simulation on transistor level |
| title_exact_search | Partitioning VLSI circuits for parallel simulation on transistor level |
| title_full | Partitioning VLSI circuits for parallel simulation on transistor level Norbert Fröhlich ; Rolf Schlagenhaft ; Josef Fleischmann |
| title_fullStr | Partitioning VLSI circuits for parallel simulation on transistor level Norbert Fröhlich ; Rolf Schlagenhaft ; Josef Fleischmann |
| title_full_unstemmed | Partitioning VLSI circuits for parallel simulation on transistor level Norbert Fröhlich ; Rolf Schlagenhaft ; Josef Fleischmann |
| title_short | Partitioning VLSI circuits for parallel simulation on transistor level |
| title_sort | partitioning vlsi circuits for parallel simulation on transistor level |
| volume_link | (DE-604)BV004627888 |
| work_keys_str_mv | AT frohlichnorbert partitioningvlsicircuitsforparallelsimulationontransistorlevel AT schlagenhaftrolf partitioningvlsicircuitsforparallelsimulationontransistorlevel AT fleischmannjosef partitioningvlsicircuitsforparallelsimulationontransistorlevel |
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Handapparate (nicht verfügbar)
| Signatur: |
0834 IB.212
Lageplan |
|---|---|
| Exemplar 1 | Dauerhaft ausgeliehen Ausgeliehen |