Quick turnaround ASIC design in VHDL: core-based behavioral synthesis
Gespeichert in:
| Beteiligte Personen: | , , |
|---|---|
| Format: | Buch |
| Sprache: | Nichtbestimmte Sprache |
| Veröffentlicht: |
Boston [u.a.]
Kluwer
1996
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
367 |
| Schlagwörter: | |
| Umfang: | XVIII, 180 S. Ill., graph. Darst. |
| ISBN: | 0792397444 |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV011113075 | ||
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| 041 | |a und | ||
| 049 | |a DE-91 |a DE-91G | ||
| 084 | |a ELT 360f |2 stub | ||
| 084 | |a DAT 190f |2 stub | ||
| 100 | 1 | |a BenRomdhane, Mohamed S. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Quick turnaround ASIC design in VHDL |b core-based behavioral synthesis |c Mohamed S. Ben Romdhane ; Vijay K. Madisetti ; John W. Hines |
| 246 | 1 | 3 | |a Quick-turnaround ASIC design in VHDL |
| 264 | 1 | |a Boston [u.a.] |b Kluwer |c 1996 | |
| 300 | |a XVIII, 180 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a The Kluwer international series in engineering and computer science |v 367 | |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Kundenspezifische Schaltung |0 (DE-588)4122250-7 |D s |
| 689 | 0 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
| 689 | 0 | 2 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Madisetti, Vijay K. |e Verfasser |4 aut | |
| 700 | 1 | |a Hines, John W. |e Verfasser |4 aut | |
| 830 | 0 | |a The Kluwer international series in engineering and computer science |v 367 |w (DE-604)BV023545171 |9 367 | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007446214 | |
Datensatz im Suchindex
| DE-BY-TUM_call_number | 0102 ELT 360f 2001 A 7334 |
|---|---|
| DE-BY-TUM_katkey | 780596 |
| DE-BY-TUM_location | 01 |
| DE-BY-TUM_media_number | 040020484844 |
| _version_ | 1821938856792948737 |
| any_adam_object | |
| author | BenRomdhane, Mohamed S. Madisetti, Vijay K. Hines, John W. |
| author_facet | BenRomdhane, Mohamed S. Madisetti, Vijay K. Hines, John W. |
| author_role | aut aut aut |
| author_sort | BenRomdhane, Mohamed S. |
| author_variant | m s b ms msb v k m vk vkm j w h jw jwh |
| building | Verbundindex |
| bvnumber | BV011113075 |
| classification_tum | ELT 360f DAT 190f |
| ctrlnum | (OCoLC)246512557 (DE-599)BVBBV011113075 |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV011113075 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T10:06:31Z |
| institution | BVB |
| isbn | 0792397444 |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007446214 |
| oclc_num | 246512557 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-91G DE-BY-TUM |
| owner_facet | DE-91 DE-BY-TUM DE-91G DE-BY-TUM |
| physical | XVIII, 180 S. Ill., graph. Darst. |
| publishDate | 1996 |
| publishDateSearch | 1996 |
| publishDateSort | 1996 |
| publisher | Kluwer |
| record_format | marc |
| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spellingShingle | BenRomdhane, Mohamed S. Madisetti, Vijay K. Hines, John W. Quick turnaround ASIC design in VHDL core-based behavioral synthesis The Kluwer international series in engineering and computer science VHDL (DE-588)4254792-1 gnd Entwurf (DE-588)4121208-3 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| subject_GND | (DE-588)4254792-1 (DE-588)4121208-3 (DE-588)4122250-7 |
| title | Quick turnaround ASIC design in VHDL core-based behavioral synthesis |
| title_alt | Quick-turnaround ASIC design in VHDL |
| title_auth | Quick turnaround ASIC design in VHDL core-based behavioral synthesis |
| title_exact_search | Quick turnaround ASIC design in VHDL core-based behavioral synthesis |
| title_full | Quick turnaround ASIC design in VHDL core-based behavioral synthesis Mohamed S. Ben Romdhane ; Vijay K. Madisetti ; John W. Hines |
| title_fullStr | Quick turnaround ASIC design in VHDL core-based behavioral synthesis Mohamed S. Ben Romdhane ; Vijay K. Madisetti ; John W. Hines |
| title_full_unstemmed | Quick turnaround ASIC design in VHDL core-based behavioral synthesis Mohamed S. Ben Romdhane ; Vijay K. Madisetti ; John W. Hines |
| title_short | Quick turnaround ASIC design in VHDL |
| title_sort | quick turnaround asic design in vhdl core based behavioral synthesis |
| title_sub | core-based behavioral synthesis |
| topic | VHDL (DE-588)4254792-1 gnd Entwurf (DE-588)4121208-3 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| topic_facet | VHDL Entwurf Kundenspezifische Schaltung |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT benromdhanemohameds quickturnaroundasicdesigninvhdlcorebasedbehavioralsynthesis AT madisettivijayk quickturnaroundasicdesigninvhdlcorebasedbehavioralsynthesis AT hinesjohnw quickturnaroundasicdesigninvhdlcorebasedbehavioralsynthesis AT benromdhanemohameds quickturnaroundasicdesigninvhdl AT madisettivijayk quickturnaroundasicdesigninvhdl AT hinesjohnw quickturnaroundasicdesigninvhdl |
Paper/Kapitel scannen lassen
Teilbibliothek Mathematik & Informatik
| Signatur: |
0102 ELT 360f 2001 A 7334 Lageplan |
|---|---|
| Exemplar 1 | Ausleihbar Am Standort |