Logic synthesis and verification algorithms:
Gespeichert in:
| Beteiligte Personen: | , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Boston [u.a.]
Kluwer
1996
|
| Schlagwörter: | |
| Umfang: | XXXII, 564 S. graph. Darst. |
| ISBN: | 0792397460 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV011021800 | ||
| 003 | DE-604 | ||
| 005 | 20020820 | ||
| 007 | t| | ||
| 008 | 961024s1996 xx d||| |||| 00||| eng d | ||
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| 041 | 0 | |a eng | |
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| 084 | |a ZN 4930 |0 (DE-625)157422: |2 rvk | ||
| 084 | |a ELT 273f |2 stub | ||
| 100 | 1 | |a Hachtel, Gary D. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Logic synthesis and verification algorithms |c by Gary D. Hachtel ; Fabio Somenzi |
| 264 | 1 | |a Boston [u.a.] |b Kluwer |c 1996 | |
| 300 | |a XXXII, 564 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Computer-aided design | |
| 650 | 4 | |a Integrated circuits |x Verification | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Design |x Data processing | |
| 650 | 4 | |a Logic design |x Data processing | |
| 650 | 0 | 7 | |a Logiksynthese |0 (DE-588)4348178-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Logischer Entwurf |0 (DE-588)4168051-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Logiksynthese |0 (DE-588)4348178-4 |D s |
| 689 | 1 | |5 DE-604 | |
| 700 | 1 | |a Somenzi, Fabio |e Verfasser |4 aut | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007378918 | |
Datensatz im Suchindex
| DE-BY-TUM_call_number | 0102 ELT 273f 2001 A 17042 0832 717 0834 CD.363 |
|---|---|
| DE-BY-TUM_katkey | 771652 |
| DE-BY-TUM_location | 01 LSB |
| DE-BY-TUM_media_number | 040020201898 TEMP3000902 TEMP3000901 |
| _version_ | 1821938596482908160 |
| any_adam_object | |
| author | Hachtel, Gary D. Somenzi, Fabio |
| author_facet | Hachtel, Gary D. Somenzi, Fabio |
| author_role | aut aut |
| author_sort | Hachtel, Gary D. |
| author_variant | g d h gd gdh f s fs |
| building | Verbundindex |
| bvnumber | BV011021800 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.75 |
| callnumber-search | TK7874.75 |
| callnumber-sort | TK 47874.75 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4930 |
| classification_tum | ELT 273f |
| ctrlnum | (OCoLC)636176944 (DE-599)BVBBV011021800 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV011021800 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T10:04:58Z |
| institution | BVB |
| isbn | 0792397460 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007378918 |
| oclc_num | 636176944 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-91G DE-BY-TUM DE-29T DE-92 |
| owner_facet | DE-91 DE-BY-TUM DE-91G DE-BY-TUM DE-29T DE-92 |
| physical | XXXII, 564 S. graph. Darst. |
| publishDate | 1996 |
| publishDateSearch | 1996 |
| publishDateSort | 1996 |
| publisher | Kluwer |
| record_format | marc |
| spellingShingle | Hachtel, Gary D. Somenzi, Fabio Logic synthesis and verification algorithms Datenverarbeitung Computer-aided design Integrated circuits Verification Integrated circuits Very large scale integration Design Data processing Logic design Data processing Logiksynthese (DE-588)4348178-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
| subject_GND | (DE-588)4348178-4 (DE-588)4168051-0 |
| title | Logic synthesis and verification algorithms |
| title_auth | Logic synthesis and verification algorithms |
| title_exact_search | Logic synthesis and verification algorithms |
| title_full | Logic synthesis and verification algorithms by Gary D. Hachtel ; Fabio Somenzi |
| title_fullStr | Logic synthesis and verification algorithms by Gary D. Hachtel ; Fabio Somenzi |
| title_full_unstemmed | Logic synthesis and verification algorithms by Gary D. Hachtel ; Fabio Somenzi |
| title_short | Logic synthesis and verification algorithms |
| title_sort | logic synthesis and verification algorithms |
| topic | Datenverarbeitung Computer-aided design Integrated circuits Verification Integrated circuits Very large scale integration Design Data processing Logic design Data processing Logiksynthese (DE-588)4348178-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
| topic_facet | Datenverarbeitung Computer-aided design Integrated circuits Verification Integrated circuits Very large scale integration Design Data processing Logic design Data processing Logiksynthese Logischer Entwurf |
| work_keys_str_mv | AT hachtelgaryd logicsynthesisandverificationalgorithms AT somenzifabio logicsynthesisandverificationalgorithms |
Paper/Kapitel scannen lassen
Teilbibliothek Mathematik & Informatik
| Signatur: |
0102 ELT 273f 2001 A 17042
Lageplan |
|---|---|
| Exemplar 1 | Ausleihbar Am Standort |
Handapparate (nicht verfügbar)
| Signatur: |
0832 717
Lageplan 0834 CD.363 Lageplan |
|---|---|
| Exemplar 1 | Dauerhaft ausgeliehen Ausgeliehen |
| Exemplar 1 | Dauerhaft ausgeliehen Ausgeliehen |