Logic synthesis for field programmable gate arrays:
Gespeichert in:
| Beteiligte Personen: | , , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Boston u.a.
Kluwer
1995
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
324 |
| Schlagwörter: | |
| Umfang: | XV, 427 S. graph. Darst. |
| ISBN: | 0792395964 |
Internformat
MARC
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| 100 | 1 | |a Murgai, Rajeev |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Logic synthesis for field programmable gate arrays |c by Rajeev Murgai ; Robert K. Brayton ; Alberto Sangiovanni-Vincentelli |
| 246 | 1 | 3 | |a Logic synthesis for field-programmable gate arrays |
| 264 | 1 | |a Boston u.a. |b Kluwer |c 1995 | |
| 300 | |a XV, 427 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
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| 650 | 7 | |a Circuits intégrés - Conception et construction |2 ram | |
| 650 | 7 | |a Réseaux logiques programmables |2 ram | |
| 650 | 4 | |a Field programmable gate arrays | |
| 650 | 4 | |a Programmable array logic | |
| 700 | 1 | |a Brayton, Robert K. |e Verfasser |4 aut | |
| 700 | 1 | |a Sangiovanni-Vincentelli, Alberto |e Verfasser |4 aut | |
| 830 | 0 | |a The Kluwer international series in engineering and computer science |v 324 |w (DE-604)BV023545171 |9 324 | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007034763 | |
Datensatz im Suchindex
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| author | Murgai, Rajeev Brayton, Robert K. Sangiovanni-Vincentelli, Alberto |
| author_facet | Murgai, Rajeev Brayton, Robert K. Sangiovanni-Vincentelli, Alberto |
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| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
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| id | DE-604.BV010552788 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T09:56:31Z |
| institution | BVB |
| isbn | 0792395964 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007034763 |
| oclc_num | 32589357 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-91 DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM DE-91 DE-BY-TUM |
| physical | XV, 427 S. graph. Darst. |
| publishDate | 1995 |
| publishDateSearch | 1995 |
| publishDateSort | 1995 |
| publisher | Kluwer |
| record_format | marc |
| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spellingShingle | Murgai, Rajeev Brayton, Robert K. Sangiovanni-Vincentelli, Alberto Logic synthesis for field programmable gate arrays The Kluwer international series in engineering and computer science Circuits intégrés - Conception et construction ram Réseaux logiques programmables ram Field programmable gate arrays Programmable array logic |
| title | Logic synthesis for field programmable gate arrays |
| title_alt | Logic synthesis for field-programmable gate arrays |
| title_auth | Logic synthesis for field programmable gate arrays |
| title_exact_search | Logic synthesis for field programmable gate arrays |
| title_full | Logic synthesis for field programmable gate arrays by Rajeev Murgai ; Robert K. Brayton ; Alberto Sangiovanni-Vincentelli |
| title_fullStr | Logic synthesis for field programmable gate arrays by Rajeev Murgai ; Robert K. Brayton ; Alberto Sangiovanni-Vincentelli |
| title_full_unstemmed | Logic synthesis for field programmable gate arrays by Rajeev Murgai ; Robert K. Brayton ; Alberto Sangiovanni-Vincentelli |
| title_short | Logic synthesis for field programmable gate arrays |
| title_sort | logic synthesis for field programmable gate arrays |
| topic | Circuits intégrés - Conception et construction ram Réseaux logiques programmables ram Field programmable gate arrays Programmable array logic |
| topic_facet | Circuits intégrés - Conception et construction Réseaux logiques programmables Field programmable gate arrays Programmable array logic |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT murgairajeev logicsynthesisforfieldprogrammablegatearrays AT braytonrobertk logicsynthesisforfieldprogrammablegatearrays AT sangiovannivincentellialberto logicsynthesisforfieldprogrammablegatearrays |
Paper/Kapitel scannen lassen
Teilbibliothek Mathematik & Informatik
| Signatur: |
0102 DAT 195f 2001 A 25774
Lageplan |
|---|---|
| Exemplar 1 | Ausleihbar Am Standort |
Handapparate (nicht verfügbar)
| Signatur: |
0832 718
Lageplan 0834 CD.367 Lageplan |
|---|---|
| Exemplar 1 | Dauerhaft ausgeliehen Ausgeliehen |
| Exemplar 1 | Dauerhaft ausgeliehen Ausgeliehen |