Fast barrier synchronization hardware:
Gespeichert in:
| Beteiligte Personen: | , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Urbana, Ill.
1990
|
| Schriftenreihe: | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report
986 |
| Schlagwörter: | |
| Abstract: | Abstract: "Many recent studies have considered the importance of barrier synchronization overhead on parallel loop performance, especially for large-scale parallel machines. This paper describes a hardware scheme for supporting fast barrier synchronization. It allows barrier synchronization to be performed within a single instruction cycle for moderately sized systems, and is scalable with logarithmic increase in synchronization time. It supports a large number of concurrent barriers, and can also be used to support a number of different barrier synchronization schemes. Simulation results show that under reasonable assumptions, this hardware can decrease parallel loop execution time significantly, especially for statically scheduled loops." |
| Umfang: | 27 S. |
Internformat
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| 100 | 1 | |a Beckmann, Carl |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Fast barrier synchronization hardware |c Carl Beckmann and Constantine Polychronopoulos |
| 264 | 1 | |a Urbana, Ill. |c 1990 | |
| 300 | |a 27 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |v 986 | |
| 520 | 3 | |a Abstract: "Many recent studies have considered the importance of barrier synchronization overhead on parallel loop performance, especially for large-scale parallel machines. This paper describes a hardware scheme for supporting fast barrier synchronization. It allows barrier synchronization to be performed within a single instruction cycle for moderately sized systems, and is scalable with logarithmic increase in synchronization time. It supports a large number of concurrent barriers, and can also be used to support a number of different barrier synchronization schemes. Simulation results show that under reasonable assumptions, this hardware can decrease parallel loop execution time significantly, especially for statically scheduled loops." | |
| 650 | 4 | |a Parallel processing (Electronic computers) | |
| 650 | 4 | |a Synchronization | |
| 700 | 1 | |a Polychronopoulos, Constantine D. |d 1958- |e Verfasser |0 (DE-588)120999773 |4 aut | |
| 830 | 0 | |a Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |v 986 |w (DE-604)BV008930033 |9 986 | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-005925543 | |
Datensatz im Suchindex
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| author | Beckmann, Carl Polychronopoulos, Constantine D. 1958- |
| author_GND | (DE-588)120999773 |
| author_facet | Beckmann, Carl Polychronopoulos, Constantine D. 1958- |
| author_role | aut aut |
| author_sort | Beckmann, Carl |
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| bvnumber | BV008973891 |
| ctrlnum | (OCoLC)23451038 (DE-599)BVBBV008973891 |
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| id | DE-604.BV008973891 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T09:29:45Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-005925543 |
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| physical | 27 S. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
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| series | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |
| series2 | Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report |
| spelling | Beckmann, Carl Verfasser aut Fast barrier synchronization hardware Carl Beckmann and Constantine Polychronopoulos Urbana, Ill. 1990 27 S. txt rdacontent n rdamedia nc rdacarrier Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report 986 Abstract: "Many recent studies have considered the importance of barrier synchronization overhead on parallel loop performance, especially for large-scale parallel machines. This paper describes a hardware scheme for supporting fast barrier synchronization. It allows barrier synchronization to be performed within a single instruction cycle for moderately sized systems, and is scalable with logarithmic increase in synchronization time. It supports a large number of concurrent barriers, and can also be used to support a number of different barrier synchronization schemes. Simulation results show that under reasonable assumptions, this hardware can decrease parallel loop execution time significantly, especially for statically scheduled loops." Parallel processing (Electronic computers) Synchronization Polychronopoulos, Constantine D. 1958- Verfasser (DE-588)120999773 aut Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report 986 (DE-604)BV008930033 986 |
| spellingShingle | Beckmann, Carl Polychronopoulos, Constantine D. 1958- Fast barrier synchronization hardware Center for Supercomputing Research and Development <Urbana, Ill.>: CSRD report Parallel processing (Electronic computers) Synchronization |
| title | Fast barrier synchronization hardware |
| title_auth | Fast barrier synchronization hardware |
| title_exact_search | Fast barrier synchronization hardware |
| title_full | Fast barrier synchronization hardware Carl Beckmann and Constantine Polychronopoulos |
| title_fullStr | Fast barrier synchronization hardware Carl Beckmann and Constantine Polychronopoulos |
| title_full_unstemmed | Fast barrier synchronization hardware Carl Beckmann and Constantine Polychronopoulos |
| title_short | Fast barrier synchronization hardware |
| title_sort | fast barrier synchronization hardware |
| topic | Parallel processing (Electronic computers) Synchronization |
| topic_facet | Parallel processing (Electronic computers) Synchronization |
| volume_link | (DE-604)BV008930033 |
| work_keys_str_mv | AT beckmanncarl fastbarriersynchronizationhardware AT polychronopoulosconstantined fastbarriersynchronizationhardware |