Integrating functional and temporal domains in logic design: the false path problem and its implications
Gespeichert in:
| Beteiligte Personen: | , |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Boston u.a.
Kluwer
1991
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
139 : VLSI, computer architecture and digital signal processing |
| Schlagwörter: | |
| Umfang: | XXII, 212 S. graph. Darst. |
| ISBN: | 0792391632 |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV006379046 | ||
| 003 | DE-604 | ||
| 005 | 19931112 | ||
| 007 | t| | ||
| 008 | 930210s1991 xx d||| |||| 00||| eng d | ||
| 020 | |a 0792391632 |9 0-7923-9163-2 | ||
| 035 | |a (OCoLC)23583191 | ||
| 035 | |a (DE-599)BVBBV006379046 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-739 |a DE-20 |a DE-29T |a DE-91 | ||
| 050 | 0 | |a TK7868.L6 | |
| 082 | 0 | |a 621.39/5 |2 20 | |
| 084 | |a ST 190 |0 (DE-625)143607: |2 rvk | ||
| 084 | |a ELT 273f |2 stub | ||
| 100 | 1 | |a MacGeer, Patrick C. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Integrating functional and temporal domains in logic design |b the false path problem and its implications |c by Patrick C. McGeer and Robert K. Brayton |
| 264 | 1 | |a Boston u.a. |b Kluwer |c 1991 | |
| 300 | |a XXII, 212 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a The Kluwer international series in engineering and computer science |v 139 : VLSI, computer architecture and digital signal processing | |
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Computer-aided design | |
| 650 | 4 | |a Logic design |x Data processing | |
| 650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a Logischer Entwurf |0 (DE-588)4168051-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Brayton, Robert K. |e Verfasser |4 aut | |
| 830 | 0 | |a The Kluwer international series in engineering and computer science |v 139 : VLSI, computer architecture and digital signal processing |w (DE-604)BV023545171 |9 139 | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-004037344 | |
Datensatz im Suchindex
| DE-BY-TUM_call_number | 0001 92 A 92 0834 CD.229 0834 CD.264 |
|---|---|
| DE-BY-TUM_katkey | 580946 |
| DE-BY-TUM_location | Mag LSB |
| DE-BY-TUM_media_number | 040000921148 TEMP2922895 TEMP2922896 |
| _version_ | 1821938477096239105 |
| any_adam_object | |
| author | MacGeer, Patrick C. Brayton, Robert K. |
| author_facet | MacGeer, Patrick C. Brayton, Robert K. |
| author_role | aut aut |
| author_sort | MacGeer, Patrick C. |
| author_variant | p c m pc pcm r k b rk rkb |
| building | Verbundindex |
| bvnumber | BV006379046 |
| callnumber-first | T - Technology |
| callnumber-label | TK7868 |
| callnumber-raw | TK7868.L6 |
| callnumber-search | TK7868.L6 |
| callnumber-sort | TK 47868 L6 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 190 |
| classification_tum | ELT 273f |
| ctrlnum | (OCoLC)23583191 (DE-599)BVBBV006379046 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01755nam a2200433 cb4500</leader><controlfield tag="001">BV006379046</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">19931112 </controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">930210s1991 xx d||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0792391632</subfield><subfield code="9">0-7923-9163-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)23583191</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV006379046</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-739</subfield><subfield code="a">DE-20</subfield><subfield code="a">DE-29T</subfield><subfield code="a">DE-91</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7868.L6</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield><subfield code="2">20</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 190</subfield><subfield code="0">(DE-625)143607:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 273f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">MacGeer, Patrick C.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Integrating functional and temporal domains in logic design</subfield><subfield code="b">the false path problem and its implications</subfield><subfield code="c">by Patrick C. McGeer and Robert K. Brayton</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston u.a.</subfield><subfield code="b">Kluwer</subfield><subfield code="c">1991</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXII, 212 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">The Kluwer international series in engineering and computer science</subfield><subfield code="v">139 : VLSI, computer architecture and digital signal processing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Datenverarbeitung</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Computer-aided design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic design</subfield><subfield code="x">Data processing</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Brayton, Robert K.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">The Kluwer international series in engineering and computer science</subfield><subfield code="v">139 : VLSI, computer architecture and digital signal processing</subfield><subfield code="w">(DE-604)BV023545171</subfield><subfield code="9">139</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-004037344</subfield></datafield></record></collection> |
| id | DE-604.BV006379046 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T08:47:46Z |
| institution | BVB |
| isbn | 0792391632 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-004037344 |
| oclc_num | 23583191 |
| open_access_boolean | |
| owner | DE-739 DE-20 DE-29T DE-91 DE-BY-TUM |
| owner_facet | DE-739 DE-20 DE-29T DE-91 DE-BY-TUM |
| physical | XXII, 212 S. graph. Darst. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| publisher | Kluwer |
| record_format | marc |
| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spellingShingle | MacGeer, Patrick C. Brayton, Robert K. Integrating functional and temporal domains in logic design the false path problem and its implications The Kluwer international series in engineering and computer science Datenverarbeitung Integrated circuits Very large scale integration Computer-aided design Logic design Data processing Logischer Entwurf (DE-588)4168051-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4168051-0 (DE-588)4117388-0 |
| title | Integrating functional and temporal domains in logic design the false path problem and its implications |
| title_auth | Integrating functional and temporal domains in logic design the false path problem and its implications |
| title_exact_search | Integrating functional and temporal domains in logic design the false path problem and its implications |
| title_full | Integrating functional and temporal domains in logic design the false path problem and its implications by Patrick C. McGeer and Robert K. Brayton |
| title_fullStr | Integrating functional and temporal domains in logic design the false path problem and its implications by Patrick C. McGeer and Robert K. Brayton |
| title_full_unstemmed | Integrating functional and temporal domains in logic design the false path problem and its implications by Patrick C. McGeer and Robert K. Brayton |
| title_short | Integrating functional and temporal domains in logic design |
| title_sort | integrating functional and temporal domains in logic design the false path problem and its implications |
| title_sub | the false path problem and its implications |
| topic | Datenverarbeitung Integrated circuits Very large scale integration Computer-aided design Logic design Data processing Logischer Entwurf (DE-588)4168051-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Datenverarbeitung Integrated circuits Very large scale integration Computer-aided design Logic design Data processing Logischer Entwurf VLSI |
| volume_link | (DE-604)BV023545171 |
| work_keys_str_mv | AT macgeerpatrickc integratingfunctionalandtemporaldomainsinlogicdesignthefalsepathproblemanditsimplications AT braytonrobertk integratingfunctionalandtemporaldomainsinlogicdesignthefalsepathproblemanditsimplications |
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Bibliotheksmagazin
| Signatur: |
0001 92 A 92
Lageplan |
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| Exemplar 1 | Ausleihbar Am Standort |
Handapparate (nicht verfügbar)
| Signatur: |
0834 CD.229
Lageplan 0834 CD.264 Lageplan |
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| Exemplar 1 | Dauerhaft ausgeliehen Ausgeliehen |
| Exemplar 2 | Dauerhaft ausgeliehen Ausgeliehen |