A novel processor architecture based on auto data sequencing and low level parallelism:
Gespeichert in:
| Beteilige Person: | |
|---|---|
| Format: | Buch |
| Sprache: | Nichtbestimmte Sprache |
| Veröffentlicht: |
1991
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| Schlagwörter: | |
| Beschreibung: | Kaiserslautern, Univ., Diss., 1991 |
| Umfang: | 228 S. graph. Darst. |
Internformat
MARC
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| 100 | 1 | |a Hirschbiel, Alexander G. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a A novel processor architecture based on auto data sequencing and low level parallelism |c by Alexander G. Hirschbiel |
| 264 | 1 | |c 1991 | |
| 300 | |a 228 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
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Datensatz im Suchindex
| DE-BY-TUM_call_number | 0001 DA 91 2191 |
|---|---|
| DE-BY-TUM_katkey | 530117 |
| DE-BY-TUM_location | Mag |
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| author | Hirschbiel, Alexander G. |
| author_facet | Hirschbiel, Alexander G. |
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| genre_facet | Hochschulschrift |
| id | DE-604.BV004533367 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T08:19:12Z |
| institution | BVB |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-002791179 |
| oclc_num | 256027440 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-29T DE-706 |
| owner_facet | DE-91 DE-BY-TUM DE-29T DE-706 |
| physical | 228 S. graph. Darst. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| record_format | marc |
| spellingShingle | Hirschbiel, Alexander G. A novel processor architecture based on auto data sequencing and low level parallelism Parallelverarbeitung (DE-588)4075860-6 gnd Xputer (DE-588)4381711-7 gnd Architektur Informatik (DE-588)4139374-0 gnd |
| subject_GND | (DE-588)4075860-6 (DE-588)4381711-7 (DE-588)4139374-0 (DE-588)4113937-9 |
| title | A novel processor architecture based on auto data sequencing and low level parallelism |
| title_auth | A novel processor architecture based on auto data sequencing and low level parallelism |
| title_exact_search | A novel processor architecture based on auto data sequencing and low level parallelism |
| title_full | A novel processor architecture based on auto data sequencing and low level parallelism by Alexander G. Hirschbiel |
| title_fullStr | A novel processor architecture based on auto data sequencing and low level parallelism by Alexander G. Hirschbiel |
| title_full_unstemmed | A novel processor architecture based on auto data sequencing and low level parallelism by Alexander G. Hirschbiel |
| title_short | A novel processor architecture based on auto data sequencing and low level parallelism |
| title_sort | a novel processor architecture based on auto data sequencing and low level parallelism |
| topic | Parallelverarbeitung (DE-588)4075860-6 gnd Xputer (DE-588)4381711-7 gnd Architektur Informatik (DE-588)4139374-0 gnd |
| topic_facet | Parallelverarbeitung Xputer Architektur Informatik Hochschulschrift |
| work_keys_str_mv | AT hirschbielalexanderg anovelprocessorarchitecturebasedonautodatasequencingandlowlevelparallelism |
Paper/Kapitel scannen lassen
Bibliotheksmagazin
| Signatur: |
0001 DA 91 2191
Lageplan |
|---|---|
| Exemplar 1 | Ausleihbar Am Standort |