APA-Zitierstil (7. Ausg.)

Davie, B. S. (1988). A formal, hierarchical design and validation methodology for VLSI. Univ. of Edinburgh, Dep. of Computer Sci.

Chicago-Zitierstil (17. Ausg.)

Davie, Bruce S. A Formal, Hierarchical Design and Validation Methodology for VLSI. Edinburgh: Univ. of Edinburgh, Dep. of Computer Sci, 1988.

MLA-Zitierstil (9. Ausg.)

Davie, Bruce S. A Formal, Hierarchical Design and Validation Methodology for VLSI. Univ. of Edinburgh, Dep. of Computer Sci, 1988.