A formal, hierarchical design and validation methodology for VLSI:
Gespeichert in:
| Beteilige Person: | |
|---|---|
| Format: | Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
Edinburgh
Univ. of Edinburgh, Dep. of Computer Sci.
1988
|
| Schriftenreihe: | University <Edinburgh> / Department of Computer Science: Thesis
55 |
| Schlagwörter: | |
| Beschreibung: | Edinburgh, Univ., Diss., 1988 |
| Umfang: | 234 S. |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV004219098 | ||
| 003 | DE-604 | ||
| 005 | 19951023 | ||
| 007 | t| | ||
| 008 | 910129s1988 xx m||| 00||| eng d | ||
| 035 | |a (OCoLC)20111970 | ||
| 035 | |a (DE-599)BVBBV004219098 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G | ||
| 084 | |a ELT 355d |2 stub | ||
| 088 | |a CST 55 88 | ||
| 100 | 1 | |a Davie, Bruce S. |e Verfasser |0 (DE-588)122327535 |4 aut | |
| 245 | 1 | 0 | |a A formal, hierarchical design and validation methodology for VLSI |
| 246 | 1 | 3 | |a CST 55 88 |
| 264 | 1 | |a Edinburgh |b Univ. of Edinburgh, Dep. of Computer Sci. |c 1988 | |
| 300 | |a 234 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a University <Edinburgh> / Department of Computer Science: Thesis |v 55 | |
| 500 | |a Edinburgh, Univ., Diss., 1988 | ||
| 650 | 7 | |a Circuits |2 sigle | |
| 650 | 7 | |a Computer software |2 sigle | |
| 650 | 7 | |a Reliability and quality control |2 sigle | |
| 650 | 4 | |a Computer-aided design | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration | |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 810 | 2 | |a Department of Computer Science: Thesis |t University <Edinburgh> |v 55 |w (DE-604)BV008928181 |9 55 | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-002626927 | |
Datensatz im Suchindex
| DE-BY-TUM_call_number | 0111 2001 B 6030-55 |
|---|---|
| DE-BY-TUM_katkey | 512463 |
| DE-BY-TUM_location | 01 |
| DE-BY-TUM_media_number | 040010602165 |
| _version_ | 1821937524122058752 |
| any_adam_object | |
| author | Davie, Bruce S. |
| author_GND | (DE-588)122327535 |
| author_facet | Davie, Bruce S. |
| author_role | aut |
| author_sort | Davie, Bruce S. |
| author_variant | b s d bs bsd |
| building | Verbundindex |
| bvnumber | BV004219098 |
| classification_tum | ELT 355d |
| ctrlnum | (OCoLC)20111970 (DE-599)BVBBV004219098 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01329nam a2200385 cb4500</leader><controlfield tag="001">BV004219098</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">19951023 </controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">910129s1988 xx m||| 00||| eng d</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)20111970</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV004219098</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 355d</subfield><subfield code="2">stub</subfield></datafield><datafield tag="088" ind1=" " ind2=" "><subfield code="a">CST 55 88</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Davie, Bruce S.</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)122327535</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">A formal, hierarchical design and validation methodology for VLSI</subfield></datafield><datafield tag="246" ind1="1" ind2="3"><subfield code="a">CST 55 88</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Edinburgh</subfield><subfield code="b">Univ. of Edinburgh, Dep. of Computer Sci.</subfield><subfield code="c">1988</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">234 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">University <Edinburgh> / Department of Computer Science: Thesis</subfield><subfield code="v">55</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Edinburgh, Univ., Diss., 1988</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Circuits</subfield><subfield code="2">sigle</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Computer software</subfield><subfield code="2">sigle</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Reliability and quality control</subfield><subfield code="2">sigle</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-aided design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4113937-9</subfield><subfield code="a">Hochschulschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="810" ind1="2" ind2=" "><subfield code="a">Department of Computer Science: Thesis</subfield><subfield code="t">University <Edinburgh></subfield><subfield code="v">55</subfield><subfield code="w">(DE-604)BV008928181</subfield><subfield code="9">55</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-002626927</subfield></datafield></record></collection> |
| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV004219098 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T08:15:01Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-002626927 |
| oclc_num | 20111970 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 234 S. |
| publishDate | 1988 |
| publishDateSearch | 1988 |
| publishDateSort | 1988 |
| publisher | Univ. of Edinburgh, Dep. of Computer Sci. |
| record_format | marc |
| series2 | University <Edinburgh> / Department of Computer Science: Thesis |
| spellingShingle | Davie, Bruce S. A formal, hierarchical design and validation methodology for VLSI Circuits sigle Computer software sigle Reliability and quality control sigle Computer-aided design Integrated circuits Very large scale integration |
| subject_GND | (DE-588)4113937-9 |
| title | A formal, hierarchical design and validation methodology for VLSI |
| title_alt | CST 55 88 |
| title_auth | A formal, hierarchical design and validation methodology for VLSI |
| title_exact_search | A formal, hierarchical design and validation methodology for VLSI |
| title_full | A formal, hierarchical design and validation methodology for VLSI |
| title_fullStr | A formal, hierarchical design and validation methodology for VLSI |
| title_full_unstemmed | A formal, hierarchical design and validation methodology for VLSI |
| title_short | A formal, hierarchical design and validation methodology for VLSI |
| title_sort | a formal hierarchical design and validation methodology for vlsi |
| topic | Circuits sigle Computer software sigle Reliability and quality control sigle Computer-aided design Integrated circuits Very large scale integration |
| topic_facet | Circuits Computer software Reliability and quality control Computer-aided design Integrated circuits Very large scale integration Hochschulschrift |
| volume_link | (DE-604)BV008928181 |
| work_keys_str_mv | AT daviebruces aformalhierarchicaldesignandvalidationmethodologyforvlsi AT daviebruces cst5588 |
Paper/Kapitel scannen lassen
Teilbibliothek Mathematik & Informatik, Berichte
| Signatur: |
0111 2001 B 6030-55
Lageplan |
|---|---|
| Exemplar 1 | Ausleihbar Am Standort |