Formal verification: an essential toolkit for modern VLSI design
Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mat...
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| Beteiligte Personen: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | Englisch |
| Veröffentlicht: |
Cambridge, MA
Morgan Kaufmann
[2023]
|
| Ausgabe: | Second edition. |
| Schlagwörter: | |
| Links: | https://learning.oreilly.com/library/view/-/9780323956130/?ar |
| Zusammenfassung: | Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes. Every chapter in the second edition has been updated to reflect evolving FV practices and advanced techniques. In addition, a new chapter, Formal Signoff on Real Projects, provides guidelines for implementing signoff quality FV, completely replacing some simulation tasks with significantly more productive FV methods. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity. |
| Beschreibung: | Includes bibliographical references and index |
| Umfang: | 1 Online-Ressource (424 Seiten) illustrations |
| ISBN: | 9780323956130 0323956130 |
Internformat
MARC
| LEADER | 00000cam a22000002 4500 | ||
|---|---|---|---|
| 001 | ZDB-30-ORH-093388128 | ||
| 003 | DE-627-1 | ||
| 005 | 20240228122015.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 230626s2023 xx |||||o 00| ||eng c | ||
| 020 | |a 9780323956130 |c electronic bk. |9 978-0-323-95613-0 | ||
| 020 | |a 0323956130 |c electronic bk. |9 0-323-95613-0 | ||
| 035 | |a (DE-627-1)093388128 | ||
| 035 | |a (DE-599)KEP093388128 | ||
| 035 | |a (ORHE)9780323956130 | ||
| 035 | |a (DE-627-1)093388128 | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rda | ||
| 041 | |a eng | ||
| 082 | 0 | |a 621.3/95 |2 23/eng/20230614 | |
| 100 | 1 | |a Seligman, Erik |e VerfasserIn |4 aut | |
| 245 | 1 | 0 | |a Formal verification |b an essential toolkit for modern VLSI design |c Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| 250 | |a Second edition. | ||
| 264 | 1 | |a Cambridge, MA |b Morgan Kaufmann |c [2023] | |
| 300 | |a 1 Online-Ressource (424 Seiten) |b illustrations | ||
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a Computermedien |b c |2 rdamedia | ||
| 338 | |a Online-Ressource |b cr |2 rdacarrier | ||
| 500 | |a Includes bibliographical references and index | ||
| 520 | |a Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes. Every chapter in the second edition has been updated to reflect evolving FV practices and advanced techniques. In addition, a new chapter, Formal Signoff on Real Projects, provides guidelines for implementing signoff quality FV, completely replacing some simulation tasks with significantly more productive FV methods. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity. | ||
| 650 | 0 | |a Electronic circuits |x Testing | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design and construction | |
| 650 | 0 | |a Verilog (Computer hardware description language) | |
| 650 | 4 | |a Verilog (Langage de description de matériel informatique) | |
| 650 | 4 | |a Electronic circuits ; Testing | |
| 650 | 4 | |a Integrated circuits ; Very large scale integration ; Design and construction | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 700 | 1 | |a Schubert, E. Thomas |d 1959- |e VerfasserIn |4 aut | |
| 700 | 1 | |a Kumar, M. V. Achutha Kiran |e VerfasserIn |4 aut | |
| 966 | 4 | 0 | |l DE-91 |p ZDB-30-ORH |q TUM_PDA_ORH |u https://learning.oreilly.com/library/view/-/9780323956130/?ar |m X:ORHE |x Aggregator |z lizenzpflichtig |3 Volltext |
| 912 | |a ZDB-30-ORH | ||
| 951 | |a BO | ||
| 912 | |a ZDB-30-ORH | ||
| 049 | |a DE-91 | ||
Datensatz im Suchindex
| DE-BY-TUM_katkey | ZDB-30-ORH-093388128 |
|---|---|
| _version_ | 1821494940873523200 |
| adam_text | |
| any_adam_object | |
| author | Seligman, Erik Schubert, E. Thomas 1959- Kumar, M. V. Achutha Kiran |
| author_facet | Seligman, Erik Schubert, E. Thomas 1959- Kumar, M. V. Achutha Kiran |
| author_role | aut aut aut |
| author_sort | Seligman, Erik |
| author_variant | e s es e t s et ets m v a k k mvak mvakk |
| building | Verbundindex |
| bvnumber | localTUM |
| collection | ZDB-30-ORH |
| ctrlnum | (DE-627-1)093388128 (DE-599)KEP093388128 (ORHE)9780323956130 |
| dewey-full | 621.3/95 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3/95 |
| dewey-search | 621.3/95 |
| dewey-sort | 3621.3 295 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Second edition. |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03054cam a22004572 4500</leader><controlfield tag="001">ZDB-30-ORH-093388128</controlfield><controlfield tag="003">DE-627-1</controlfield><controlfield tag="005">20240228122015.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">230626s2023 xx |||||o 00| ||eng c</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780323956130</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">978-0-323-95613-0</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0323956130</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">0-323-95613-0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627-1)093388128</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)KEP093388128</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ORHE)9780323956130</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627-1)093388128</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3/95</subfield><subfield code="2">23/eng/20230614</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Seligman, Erik</subfield><subfield code="e">VerfasserIn</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Formal verification</subfield><subfield code="b">an essential toolkit for modern VLSI design</subfield><subfield code="c">Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">Second edition.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Cambridge, MA</subfield><subfield code="b">Morgan Kaufmann</subfield><subfield code="c">[2023]</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (424 Seiten)</subfield><subfield code="b">illustrations</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references and index</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes. Every chapter in the second edition has been updated to reflect evolving FV practices and advanced techniques. In addition, a new chapter, Formal Signoff on Real Projects, provides guidelines for implementing signoff quality FV, completely replacing some simulation tasks with significantly more productive FV methods. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity.</subfield></datafield><datafield tag="650" ind1=" " ind2="0"><subfield code="a">Electronic circuits</subfield><subfield code="x">Testing</subfield></datafield><datafield tag="650" ind1=" " ind2="0"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="0"><subfield code="a">Verilog (Computer hardware description language)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Verilog (Langage de description de matériel informatique)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits ; Testing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits ; Very large scale integration ; Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Verilog (Computer hardware description language)</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Schubert, E. Thomas</subfield><subfield code="d">1959-</subfield><subfield code="e">VerfasserIn</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kumar, M. V. Achutha Kiran</subfield><subfield code="e">VerfasserIn</subfield><subfield code="4">aut</subfield></datafield><datafield tag="966" ind1="4" ind2="0"><subfield code="l">DE-91</subfield><subfield code="p">ZDB-30-ORH</subfield><subfield code="q">TUM_PDA_ORH</subfield><subfield code="u">https://learning.oreilly.com/library/view/-/9780323956130/?ar</subfield><subfield code="m">X:ORHE</subfield><subfield code="x">Aggregator</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-30-ORH</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">BO</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-30-ORH</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield></datafield></record></collection> |
| id | ZDB-30-ORH-093388128 |
| illustrated | Illustrated |
| indexdate | 2025-01-17T11:22:22Z |
| institution | BVB |
| isbn | 9780323956130 0323956130 |
| language | English |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM |
| owner_facet | DE-91 DE-BY-TUM |
| physical | 1 Online-Ressource (424 Seiten) illustrations |
| psigel | ZDB-30-ORH TUM_PDA_ORH ZDB-30-ORH |
| publishDate | 2023 |
| publishDateSearch | 2023 |
| publishDateSort | 2023 |
| publisher | Morgan Kaufmann |
| record_format | marc |
| spelling | Seligman, Erik VerfasserIn aut Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar Second edition. Cambridge, MA Morgan Kaufmann [2023] 1 Online-Ressource (424 Seiten) illustrations Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Includes bibliographical references and index Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes. Every chapter in the second edition has been updated to reflect evolving FV practices and advanced techniques. In addition, a new chapter, Formal Signoff on Real Projects, provides guidelines for implementing signoff quality FV, completely replacing some simulation tasks with significantly more productive FV methods. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity. Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Verilog (Langage de description de matériel informatique) Electronic circuits ; Testing Integrated circuits ; Very large scale integration ; Design and construction Schubert, E. Thomas 1959- VerfasserIn aut Kumar, M. V. Achutha Kiran VerfasserIn aut |
| spellingShingle | Seligman, Erik Schubert, E. Thomas 1959- Kumar, M. V. Achutha Kiran Formal verification an essential toolkit for modern VLSI design Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Verilog (Langage de description de matériel informatique) Electronic circuits ; Testing Integrated circuits ; Very large scale integration ; Design and construction |
| title | Formal verification an essential toolkit for modern VLSI design |
| title_auth | Formal verification an essential toolkit for modern VLSI design |
| title_exact_search | Formal verification an essential toolkit for modern VLSI design |
| title_full | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_fullStr | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_full_unstemmed | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_short | Formal verification |
| title_sort | formal verification an essential toolkit for modern vlsi design |
| title_sub | an essential toolkit for modern VLSI design |
| topic | Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Verilog (Langage de description de matériel informatique) Electronic circuits ; Testing Integrated circuits ; Very large scale integration ; Design and construction |
| topic_facet | Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Verilog (Langage de description de matériel informatique) Electronic circuits ; Testing Integrated circuits ; Very large scale integration ; Design and construction |
| work_keys_str_mv | AT seligmanerik formalverificationanessentialtoolkitformodernvlsidesign AT schubertethomas formalverificationanessentialtoolkitformodernvlsidesign AT kumarmvachuthakiran formalverificationanessentialtoolkitformodernvlsidesign |