Design Automation for Timing-Driven Layout Synthesis:
Moore's law [Noy77], which predicted that the number of devices in tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be gun to slow down somewhat due to the physical limits of integration technology. Advances in...
Gespeichert in:
| Beteiligte Personen: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | Englisch |
| Veröffentlicht: |
Boston, MA
Springer US
1993
|
| Schriftenreihe: | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
198 |
| Schlagwörter: | |
| Links: | https://doi.org/10.1007/978-1-4615-3178-4 https://doi.org/10.1007/978-1-4615-3178-4 |
| Zusammenfassung: | Moore's law [Noy77], which predicted that the number of devices in tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of chip designers would have to increase at the same rate as the level of integration. Without such an increase in productivity, the design of complex systems might not be achievable within a reasonable time-frame. The rapidly increasing complexity of VLSI circuits has made de- 1 2 INTRODUCTION sign automation an absolute necessity, since the required increase in productivity can only be accomplished with the use of sophisticated design tools. Such tools also enable designers to perform trade-off analyses of different logic implementations and to make well-informed design decisions |
| Umfang: | 1 Online-Ressource (XXI, 269 p) |
| ISBN: | 9781461531784 |
| DOI: | 10.1007/978-1-4615-3178-4 |
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| spelling | Sapatnekar, Sachin S. Verfasser aut Design Automation for Timing-Driven Layout Synthesis by Sachin S. Sapatnekar, Sung-Mo Kang Boston, MA Springer US 1993 1 Online-Ressource (XXI, 269 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 198 Moore's law [Noy77], which predicted that the number of devices in tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of chip designers would have to increase at the same rate as the level of integration. Without such an increase in productivity, the design of complex systems might not be achievable within a reasonable time-frame. The rapidly increasing complexity of VLSI circuits has made de- 1 2 INTRODUCTION sign automation an absolute necessity, since the required increase in productivity can only be accomplished with the use of sophisticated design tools. Such tools also enable designers to perform trade-off analyses of different logic implementations and to make well-informed design decisions Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Layout Mikroelektronik (DE-588)4264372-7 gnd rswk-swf Layout Mikroelektronik (DE-588)4264372-7 s Entwurfsautomation (DE-588)4312536-0 s 1\p DE-604 Kang, Sung-Mo aut Erscheint auch als Druck-Ausgabe 9781461363934 https://doi.org/10.1007/978-1-4615-3178-4 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Sapatnekar, Sachin S. Kang, Sung-Mo Design Automation for Timing-Driven Layout Synthesis Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Entwurfsautomation (DE-588)4312536-0 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd |
| subject_GND | (DE-588)4312536-0 (DE-588)4264372-7 |
| title | Design Automation for Timing-Driven Layout Synthesis |
| title_auth | Design Automation for Timing-Driven Layout Synthesis |
| title_exact_search | Design Automation for Timing-Driven Layout Synthesis |
| title_full | Design Automation for Timing-Driven Layout Synthesis by Sachin S. Sapatnekar, Sung-Mo Kang |
| title_fullStr | Design Automation for Timing-Driven Layout Synthesis by Sachin S. Sapatnekar, Sung-Mo Kang |
| title_full_unstemmed | Design Automation for Timing-Driven Layout Synthesis by Sachin S. Sapatnekar, Sung-Mo Kang |
| title_short | Design Automation for Timing-Driven Layout Synthesis |
| title_sort | design automation for timing driven layout synthesis |
| topic | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Entwurfsautomation (DE-588)4312536-0 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Entwurfsautomation Layout Mikroelektronik |
| url | https://doi.org/10.1007/978-1-4615-3178-4 |
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