High-Speed Clock Network Design:

High-Speed Clock Network Design is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters

Gespeichert in:
Bibliographische Detailangaben
Beteilige Person: Zhu, Qing K. (VerfasserIn)
Format: Elektronisch E-Book
Sprache:Englisch
Veröffentlicht: Boston, MA Springer US 2003
Schlagwörter:
Links:https://doi.org/10.1007/978-1-4757-3705-9
https://doi.org/10.1007/978-1-4757-3705-9
https://doi.org/10.1007/978-1-4757-3705-9
Zusammenfassung:High-Speed Clock Network Design is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters
Umfang:1 Online-Ressource (VIII, 188 p)
ISBN:9781475737059
DOI:10.1007/978-1-4757-3705-9