System-on-a-Chip Verification: Methodology and Techniques
System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level...
Gespeichert in:
| Beteiligte Personen: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | Englisch |
| Veröffentlicht: |
Boston, MA
Springer US
2002
|
| Schlagwörter: | |
| Links: | https://doi.org/10.1007/b116428 https://doi.org/10.1007/b116428 https://doi.org/10.1007/b116428 |
| Zusammenfassung: | System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application. System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter: Explanation of the objective involved in performing verification after a given design step; Features of options available; When to use a particular option; How to select an option; and Limitations of the option. This exciting new book will be of interest to all designers and test professionals |
| Umfang: | 1 Online-Ressource (XX, 372 p. 22 illus) |
| ISBN: | 9780306469954 |
| DOI: | 10.1007/b116428 |
Internformat
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| indexdate | 2024-12-20T18:19:18Z |
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| isbn | 9780306469954 |
| language | English |
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| spelling | Rashinkar, Prakash Verfasser aut System-on-a-Chip Verification Methodology and Techniques by Prakash Rashinkar, Peter Paterson, Leena Singh Boston, MA Springer US 2002 1 Online-Ressource (XX, 372 p. 22 illus) txt rdacontent c rdamedia cr rdacarrier System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application. System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter: Explanation of the objective involved in performing verification after a given design step; Features of options available; When to use a particular option; How to select an option; and Limitations of the option. This exciting new book will be of interest to all designers and test professionals Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Computing Methodologies Electrical Engineering Computers Computer-aided engineering Electrical engineering Electronic circuits Softwareentwicklung (DE-588)4116522-6 gnd rswk-swf Hardwareverifikation (DE-588)4214982-4 gnd rswk-swf Softwareentwicklung (DE-588)4116522-6 s Hardwareverifikation (DE-588)4214982-4 s 1\p DE-604 Paterson, Peter aut Singh, Leena aut Erscheint auch als Druck-Ausgabe 9780792372790 https://doi.org/10.1007/b116428 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Rashinkar, Prakash Paterson, Peter Singh, Leena System-on-a-Chip Verification Methodology and Techniques Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Computing Methodologies Electrical Engineering Computers Computer-aided engineering Electrical engineering Electronic circuits Softwareentwicklung (DE-588)4116522-6 gnd Hardwareverifikation (DE-588)4214982-4 gnd |
| subject_GND | (DE-588)4116522-6 (DE-588)4214982-4 |
| title | System-on-a-Chip Verification Methodology and Techniques |
| title_auth | System-on-a-Chip Verification Methodology and Techniques |
| title_exact_search | System-on-a-Chip Verification Methodology and Techniques |
| title_full | System-on-a-Chip Verification Methodology and Techniques by Prakash Rashinkar, Peter Paterson, Leena Singh |
| title_fullStr | System-on-a-Chip Verification Methodology and Techniques by Prakash Rashinkar, Peter Paterson, Leena Singh |
| title_full_unstemmed | System-on-a-Chip Verification Methodology and Techniques by Prakash Rashinkar, Peter Paterson, Leena Singh |
| title_short | System-on-a-Chip Verification |
| title_sort | system on a chip verification methodology and techniques |
| title_sub | Methodology and Techniques |
| topic | Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Computing Methodologies Electrical Engineering Computers Computer-aided engineering Electrical engineering Electronic circuits Softwareentwicklung (DE-588)4116522-6 gnd Hardwareverifikation (DE-588)4214982-4 gnd |
| topic_facet | Engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Computing Methodologies Electrical Engineering Computers Computer-aided engineering Electrical engineering Electronic circuits Softwareentwicklung Hardwareverifikation |
| url | https://doi.org/10.1007/b116428 |
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