Beginning FPGA: Programming Metal: Your brain on hardware
Gespeichert in:
| Beteiligte Personen: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | Englisch |
| Veröffentlicht: |
Berkeley, CA
Apress
2017
|
| Schlagwörter: | |
| Links: | https://doi.org/10.1007/978-1-4302-6248-0 https://doi.org/10.1007/978-1-4302-6248-0 https://doi.org/10.1007/978-1-4302-6248-0 https://doi.org/10.1007/978-1-4302-6248-0 https://doi.org/10.1007/978-1-4302-6248-0 https://doi.org/10.1007/978-1-4302-6248-0 https://doi.org/10.1007/978-1-4302-6248-0 https://doi.org/10.1007/978-1-4302-6248-0 https://doi.org/10.1007/978-1-4302-6248-0 https://doi.org/10.1007/978-1-4302-6248-0 https://doi.org/10.1007/978-1-4302-6248-0 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=029398953&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| Umfang: | 1 Online-Ressource (XV, 387 Seiten) 339 Illustrationen, 312 Illustrationen (farbig) |
| ISBN: | 9781430262480 |
| DOI: | 10.1007/978-1-4302-6248-0 |
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Datensatz im Suchindex
| _version_ | 1819348842539122688 |
|---|---|
| adam_text | Beginning FPGA:
Programming Metal
Your brain on hardware
Aiken Pang
Peter Membrey
ULB Darmstadt
Apress®
19691918
Contents
About the Authors xiii
About the Technical Reviewer xv
■Part I: Getting Started with FPGA 1
■Chapter 1: What Is an FPGA and What Can It Do? 3
1 1 Field-Programmable 4
111 Configuration Technology 4
1 2 Gates = Logic 5
121 The Basic Gate Design Block No 1: Logic Element 5
122 The Basic Gate Design Block No 2: Configurable 10 Block 8
123 The Basic Gate Design Block No 3: Internal RAM 8
1 3 Arrays Have Many Connections 8
1 4 What Can It Do? 9
1 5 It Can Get the Job Done Fast! 10
1 6 FPGA vs Processor 11
1 7 Summary 12
■Chapter 2: Our Weapon of Choice 13
2 1 What Weapons (FPGAs) Are Available 13
2 2 The BeMicro Max 10: Our Weapon of Choice 14
221 The Master: Altera MAX 10 FPGA 15
222 The Emissaries: BeMicro MAX 10 Board Features 17
«I CONTENTS
2 3 Other Tools 18
231 The Place to Connect Everything: The Breadboard 19
232 Making the Invisible Visible: The Multi-meter 20
2 4 Wrap-up 21
■Chapter 3: Lock and Load 23
3 1 Getting the Development Toolchain Up and Running 23
3 2 Downloading Altera Tools 24
321 Altera Toolchains 25
322 Create an Altera Account 25
323 Download the Altera Toolchains 26
3 3 Install Altera Quartus Prime Lite Edition 33
3 4 Download BeMicrol 0 files and Documentation 44
3 5 Summary 45
■Chapter 4: Hello World! 47
4 1 Launch Quartus Prime and Create a New Project 47
4 2 Write Code 61
4 3 Implement Design 69
4 4 Simulate Design 75
4 5 Burn It! 89
451 Install USB Blaster Driver 89
452 Program Design 92
4 6 Recapping What We Just Completed 97
461 Timing constraints 97
462 The Implementation 97
463 The Test Bench 101
4 7 Summary 103
471 But I Don’t have a Mercury Module! 103
■I CONTENTS
■Part II: Time Out for Theory 105
■Chapter 5: FPGA Development Timeline 107
5 1 1847—First Theory—Boolean Logic 107
5 2 1935—First Boolean Logic in Real World 107
5 3 1942—First Electronic Digital Computer 107
5 4 1960—First MOSFET 108
5 5 1960—First Practical Commercial Logic 1C Module 109
5 6 1962—First Standard Logic ICs Family 110
5 7 1963—First CMOS 110
5 8 1964—First SRAM 110
5 9 1965—The Well-Known Law: Moore’s Law 110
5 10 1970—First PROM Ill
5 11 1971—First EPROM Ill
5 12 1975—First F-PLA Ill
5 13 1978—First PAL Ill
5 14 1983—First EEPROM Ill
5 15 1983—First GAL Ill
5 16 1983—First Programming Language/Tools for Hardware 112
5 17 1985—First FPGA by Xilinx 112
5 18 FPGA vs ASIC 112
5 18 1 FPGA Advantages 112
5 18 2 FPGA Disadvantages 113
5 18 3 ASIC Advantages 113
5 18 4 ASIC Disadvantages 114
5 19 Other Technology 114
5 19 1 CPLD 114
5 19 2 Cypress-PSoC 114
5 20 Summary 115
vii
CONTENTS
■Chapter 6: VHDL101 117
6 1 It Is NOT Another Computer Language 117
6 2 VHDL File Basic Structure 118
621 Entity Declaration 118
622 Architecture Body 119
6 3 Summary 123
■Chapter 7: Number Theory for FPGAs 125
7 1 Vocabulary in VHDL 125
711 Identifiers 125
712 Reserved Words—Keywords 126
713 Signal, Variable, and Constant 128
714 Literal: Word for Word 132
7 2 Grammar in VHDL 134
721 Statements in VHDL 134
722 How to Comment 134
723 = and := sign 134
724 Begin and End 134
725 Coding Your VHDL with Style 135
7 3 Summary 135
■Chapter 8: Telling the Truth: Boolean Algebra and Truth Tables 137
8 1 Boolean Algebra 137
811 Simulation Steps for Boolean Algebra Example 2 139
812 Truth Tables 149
8 2 Standard Logic in VHDL 150
821 Standard Logic Data Types 151
822 4-Bit Adder Examples with Standard Logic Types 151
8 3 Combinational Logic Design in FPGA 157
8 4 Summary 158
CONTENTS
■Chapter 9: Simplifying Boolean Algebra for FPGA 159
9 1 Concurrent Statements 162
9 2 Conditional Signal Assignment—When/Else 162
9 3 Select Signal Assignment—With/Select 164
9 4 Process with Case Statement 167
9 5 Summary 170
■Chapter 10: Sequential Logic: IF This, THEN That 171
10 1 IF Statement 171
10 11D Flip-Flops with Clear and Preset 172
10 1 2 Shift Registers 178
10 1 3 4-Bit Up Counter Design Example 181
10 2 More Than Sequential Logic—Sequential Statements 187
10 3 VHDL Architecture Review 189
10 4 Summary 190
■Chapter 11: Combinatorial Logic: Putting It All Together on the FPGA 191
11 1 Introduction 191
11 2 First FSM Example—4-Bit Up Counter 192
11 2 1 Using Altera Quartus to Understand the FSM 196
11 3 Combinational Lock Example 199
11 3 1 Set Key Sequences 200
11 3 2 Unlock Sequences 200
11 3 3 Code for the Combinational Lock Design 201
11 3 4 Simulate the Combinational Lock with ModelSim Script 206
11 4 A Little Bit More About FSM in Digital Design 215
11 5 Wrap-up 216
11 5 1 Review FSMs 217
IX
CONTENTS
■Part III: Let’s Make Something! 219
■Chapter 12: Light Sensors: Turning a Laser Pointer into a Hi-Tech Tripwire 221
12 1 Introduction 221
12 2 Photo Resistor Circuit 101 222
12 3 BeMicro MAXI 0 LED Circuit 222
12 4 FPGA IP—Altera ADC IP (Hard IP and Soft IP) 224
12 4 1 Hard IP 225
12 4 2 Soft IP 225
12 4 3 How to Configure Your First IP 226
12 5 FPGA IP—Altera PLL IP 233
12 5 1 Generate ADC PLL IP 233
12 5 2 Generate Cascade PLL IP 237
12 6 Hi-Tech Tripwire Design Example 240
12 6 1 Light Sensor ADC Sequencer Module 241
12 6 2 Light Sensor Counter LED 244
12 6 3 Light Sensor Top Level 249
12 6 4 Add All Files to the Project and Create the Tripwire Device 253
12 6 5 Program the Tripwire Design to the FPGA 258
12 7 Summary 265
■Chapter 13: Temperature Sensors: Is It Hot in Here, or Is It Just Me? 267
13 1 Introduction 267
13 2 UART with Control Memory Map 269
13 2 1 UART IP 270
13 2 2 UART PC Software 272
13 3 I2C Communication 274
13 3 1 Basic I2C 274
13 3 2 I2C Master 274
13 3 3 Temperature Sensor—Analog Device ADT7420 276
13 3 4 I2C Slave 278
x
CONTENTS
13 4 FPGA IP—Altera PLL IP 280
13 5 PC Control Temperature Sensor Design Example 282
13 5 1 Define What Needs to Be Done—Command and Status Registers 284
13 5 2 Example Design Codes 285
13 5 3 Example Simulation Codes 292
13 5 4 Create Temperature Sensor Project Design and Program It 297
13 5 5 Hardware Setup for the Temperature Sensor Project Design 305
13 5 6 UART Software Setup—RealTerm 305
13 5 7 Command Your FPGA to Read the Temperature 307
13 6 Summary 311
■Chapter 14: How Fast Can You Run? Ask the Accelerometer! 313
14 1 Introduction 313
14 2 Steps to Build Your First Interface Module 314
14 2 1 Understanding the SPI 314
14 2 2 What Do You Need for an SPI Master Module? 314
14 2 3 Create the SPI Master Module Entity Port List 316
14 2 4 Create Processes in VHDL for the Requirements 318
14 3 PC Control Accelerometer Sensor Design Example 322
14 3 1 Add New Command and Status Registers 324
14 3 2 Create the Temperature Sensor Project Design and Program It 326
14 3 3 Example Design Codes 326
14 3 4 Hardware Setup for the Accelerator Sensor Project Design 338
14 3 5 Initialize the Accelerometer—ADXL362 338
14 4 Summary 343
■Part IV: Taking It Further: Talking to the Raspberry Pi and
LED Displays 345
■Chapter 15: Two-Way Communications with Your Raspberry Pi: SPI 347
15 1 Introduction 347
15 2 Define Our SPI Slave Interface for the Raspberry Pi 347
XI
1 CONTENTS
15 3 Design SPI Slave in FPGA 349
15 3 1 New SPI Slave Module Port List 350
15 3 2 Raspberry Pi SPI Master 0 Default Setting and Data Format 351
15 3 3 Writing VHDL for the SPI Slave 352
15 4 Create the FPGA Top-Level Design 360
15 4 1 Top-Level Design VHDL Code 361
15 4 2 Generate and Program the FPGA 363
15 5 How to Use Raspberry Pi SPI Master Interface 365
15 5 1 Python Code to Read and Write SPI Master 365
15 6 Summary 366
■Chapter 16: Up in Lights: How to Drive LED Segment Displays 367
16 1 Introduction 367
16 2 How to drive a 7 segment display 367
16 2 1 Connecting 7 segment display to FPGA 368
16 3 Designing the 7 segment display counter 371
16 3 1 Simple counter design section 372
16 327 segment decoder section 374
16 3 3 End of the counter design 374
16 4 7 Segment display example design 375
16 4 1 Code for the top level design 375
16 4 2 Generate and program the FPGA 378
16 5 Control the 7 segment counter from Raspberry Pi 378
16 6 Summary 379
Index
|
| any_adam_object | 1 |
| author | Pang, Aiken Membrey, Peter |
| author_facet | Pang, Aiken Membrey, Peter |
| author_role | aut aut |
| author_sort | Pang, Aiken |
| author_variant | a p ap p m pm |
| building | Verbundindex |
| bvnumber | BV043990745 |
| classification_rvk | ST 330 ST 190 |
| collection | ZDB-2-CWD |
| ctrlnum | (ZDB-2-CWD)978-1-4302-6248-0 (OCoLC)968330211 (DE-599)BVBBV043990745 |
| dewey-full | 004.6 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 004 - Computer science |
| dewey-raw | 004.6 |
| dewey-search | 004.6 |
| dewey-sort | 14.6 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Informatik |
| doi_str_mv | 10.1007/978-1-4302-6248-0 |
| format | Electronic eBook |
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| oclc_num | 968330211 |
| open_access_boolean | |
| owner | DE-Aug4 DE-898 DE-BY-UBR DE-M347 DE-573 DE-523 DE-859 DE-863 DE-BY-FWS DE-92 DE-862 DE-BY-FWS DE-1046 |
| owner_facet | DE-Aug4 DE-898 DE-BY-UBR DE-M347 DE-573 DE-523 DE-859 DE-863 DE-BY-FWS DE-92 DE-862 DE-BY-FWS DE-1046 |
| physical | 1 Online-Ressource (XV, 387 Seiten) 339 Illustrationen, 312 Illustrationen (farbig) |
| psigel | ZDB-2-CWD ZDB-2-CWD_2017 |
| publishDate | 2017 |
| publishDateSearch | 2017 |
| publishDateSort | 2017 |
| publisher | Apress |
| record_format | marc |
| spellingShingle | Pang, Aiken Membrey, Peter Beginning FPGA: Programming Metal Your brain on hardware Computer science Computer communication systems Computer Science Computer Communication Networks Computer Science, general Informatik Field programmable gate array (DE-588)4347749-5 gnd |
| subject_GND | (DE-588)4347749-5 |
| title | Beginning FPGA: Programming Metal Your brain on hardware |
| title_auth | Beginning FPGA: Programming Metal Your brain on hardware |
| title_exact_search | Beginning FPGA: Programming Metal Your brain on hardware |
| title_full | Beginning FPGA: Programming Metal Your brain on hardware by Aiken Pang, Peter Membrey |
| title_fullStr | Beginning FPGA: Programming Metal Your brain on hardware by Aiken Pang, Peter Membrey |
| title_full_unstemmed | Beginning FPGA: Programming Metal Your brain on hardware by Aiken Pang, Peter Membrey |
| title_short | Beginning FPGA: Programming Metal |
| title_sort | beginning fpga programming metal your brain on hardware |
| title_sub | Your brain on hardware |
| topic | Computer science Computer communication systems Computer Science Computer Communication Networks Computer Science, general Informatik Field programmable gate array (DE-588)4347749-5 gnd |
| topic_facet | Computer science Computer communication systems Computer Science Computer Communication Networks Computer Science, general Informatik Field programmable gate array |
| url | https://doi.org/10.1007/978-1-4302-6248-0 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=029398953&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT pangaiken beginningfpgaprogrammingmetalyourbrainonhardware AT membreypeter beginningfpgaprogrammingmetalyourbrainonhardware |