Quality-Driven SystemC Design:
Gespeichert in:
| Beteilige Person: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | Englisch |
| Veröffentlicht: |
Dordrecht
Springer Netherlands
2010
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| Schlagwörter: | |
| Links: | https://doi.org/10.1007/978-90-481-3631-5 https://doi.org/10.1007/978-90-481-3631-5 https://doi.org/10.1007/978-90-481-3631-5 https://doi.org/10.1007/978-90-481-3631-5 https://doi.org/10.1007/978-90-481-3631-5 |
| Beschreibung: | Faced with the steadily increasing complexity and rapidly shortening time-to-market requirements designing electronic systems is a very challenging task. To manage this situation effectively the level of abstraction in modeling has been raised during the past years in the computer aided design community. Meanwhile, for the so-called system-level design the system description language SystemC has become the de facto standard. However, while modeling from abstract to synthesizable descriptions in combination with specification concepts like Transaction Level Modeling (TLM) leads to very good results, the verification quality is poor. The two main reasons are that (1) the existing SystemC verification techniques do not escort the different abstraction levels effectively and (2) in particular the resulting quality in terms of the covered functionality is only checked manually. Hence, due to the increasing design complexity the number of undetected errors is growing rapidly. Therefore a quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results |
| Umfang: | 1 Online-Ressource (XIX, 170p) |
| ISBN: | 9789048136315 |
| DOI: | 10.1007/978-90-481-3631-5 |
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| 500 | |a Faced with the steadily increasing complexity and rapidly shortening time-to-market requirements designing electronic systems is a very challenging task. To manage this situation effectively the level of abstraction in modeling has been raised during the past years in the computer aided design community. Meanwhile, for the so-called system-level design the system description language SystemC has become the de facto standard. However, while modeling from abstract to synthesizable descriptions in combination with specification concepts like Transaction Level Modeling (TLM) leads to very good results, the verification quality is poor. The two main reasons are that (1) the existing SystemC verification techniques do not escort the different abstraction levels effectively and (2) in particular the resulting quality in terms of the covered functionality is only checked manually. Hence, due to the increasing design complexity the number of undetected errors is growing rapidly. Therefore a quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results | ||
| 505 | 0 | |a Preliminaries -- System-Level Verification -- Block-Level Verification -- Top-Level Verification -- Summary and Conclusions | |
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Datensatz im Suchindex
| _version_ | 1818979285208137728 |
|---|---|
| any_adam_object | |
| author | Große, Daniel |
| author_facet | Große, Daniel |
| author_role | aut |
| author_sort | Große, Daniel |
| author_variant | d g dg |
| building | Verbundindex |
| bvnumber | BV041889762 |
| classification_rvk | ST 250 |
| collection | ZDB-2-ENG |
| contents | Preliminaries -- System-Level Verification -- Block-Level Verification -- Top-Level Verification -- Summary and Conclusions |
| ctrlnum | (OCoLC)881654227 (DE-599)BVBBV041889762 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-90-481-3631-5 |
| format | Electronic eBook |
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| id | DE-604.BV041889762 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-20T16:57:06Z |
| institution | BVB |
| isbn | 9789048136315 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027333716 |
| oclc_num | 881654227 |
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| physical | 1 Online-Ressource (XIX, 170p) |
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| spelling | Große, Daniel Verfasser aut Quality-Driven SystemC Design by Daniel Große, Rolf Drechsler Dordrecht Springer Netherlands 2010 1 Online-Ressource (XIX, 170p) txt rdacontent c rdamedia cr rdacarrier Faced with the steadily increasing complexity and rapidly shortening time-to-market requirements designing electronic systems is a very challenging task. To manage this situation effectively the level of abstraction in modeling has been raised during the past years in the computer aided design community. Meanwhile, for the so-called system-level design the system description language SystemC has become the de facto standard. However, while modeling from abstract to synthesizable descriptions in combination with specification concepts like Transaction Level Modeling (TLM) leads to very good results, the verification quality is poor. The two main reasons are that (1) the existing SystemC verification techniques do not escort the different abstraction levels effectively and (2) in particular the resulting quality in terms of the covered functionality is only checked manually. Hence, due to the increasing design complexity the number of undetected errors is growing rapidly. Therefore a quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results Preliminaries -- System-Level Verification -- Block-Level Verification -- Top-Level Verification -- Summary and Conclusions Engineering Computer science Software engineering Systems engineering Circuits and Systems Software Engineering/Programming and Operating Systems Register-Transfer-Level Implementation Informatik Ingenieurwissenschaften SystemC (DE-588)4737678-8 gnd rswk-swf Digitales System (DE-588)4012300-5 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Model Checking (DE-588)4434799-6 gnd rswk-swf SystemC (DE-588)4737678-8 s Digitales System (DE-588)4012300-5 s Entwurfsautomation (DE-588)4312536-0 s Model Checking (DE-588)4434799-6 s 1\p DE-604 Drechsler, Rolf Sonstige oth Erscheint auch als Druckausgabe 978-90-481-3630-8 https://doi.org/10.1007/978-90-481-3631-5 Verlag Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Große, Daniel Quality-Driven SystemC Design Preliminaries -- System-Level Verification -- Block-Level Verification -- Top-Level Verification -- Summary and Conclusions Engineering Computer science Software engineering Systems engineering Circuits and Systems Software Engineering/Programming and Operating Systems Register-Transfer-Level Implementation Informatik Ingenieurwissenschaften SystemC (DE-588)4737678-8 gnd Digitales System (DE-588)4012300-5 gnd Entwurfsautomation (DE-588)4312536-0 gnd Model Checking (DE-588)4434799-6 gnd |
| subject_GND | (DE-588)4737678-8 (DE-588)4012300-5 (DE-588)4312536-0 (DE-588)4434799-6 |
| title | Quality-Driven SystemC Design |
| title_auth | Quality-Driven SystemC Design |
| title_exact_search | Quality-Driven SystemC Design |
| title_full | Quality-Driven SystemC Design by Daniel Große, Rolf Drechsler |
| title_fullStr | Quality-Driven SystemC Design by Daniel Große, Rolf Drechsler |
| title_full_unstemmed | Quality-Driven SystemC Design by Daniel Große, Rolf Drechsler |
| title_short | Quality-Driven SystemC Design |
| title_sort | quality driven systemc design |
| topic | Engineering Computer science Software engineering Systems engineering Circuits and Systems Software Engineering/Programming and Operating Systems Register-Transfer-Level Implementation Informatik Ingenieurwissenschaften SystemC (DE-588)4737678-8 gnd Digitales System (DE-588)4012300-5 gnd Entwurfsautomation (DE-588)4312536-0 gnd Model Checking (DE-588)4434799-6 gnd |
| topic_facet | Engineering Computer science Software engineering Systems engineering Circuits and Systems Software Engineering/Programming and Operating Systems Register-Transfer-Level Implementation Informatik Ingenieurwissenschaften SystemC Digitales System Entwurfsautomation Model Checking |
| url | https://doi.org/10.1007/978-90-481-3631-5 |
| work_keys_str_mv | AT großedaniel qualitydrivensystemcdesign AT drechslerrolf qualitydrivensystemcdesign |