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Verification architectures for complex real time systems:

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Bibliographic Details
Main Author:	Faber, Johannes (Author)
Format:	Thesis/Dissertation Book
Language:	English
Published:	2011
Series:	Berichte aus dem Department für Informatik der Fakultät II - Informatik, Wirtschafts- und Rechtswissenschaften 2011,3
Subjects:	Echtzeitverarbeitung CSP Hochschulschrift
Links:	http://www.informatik.uni-oldenburg.de/download/Promotionen/Faber2011.pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=024505413&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
Physical Description:	XIV, 354 S. graph. Darst.

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adam_text	IMAGE 1 CONTENTS 1. INTRODUCTION 1 1.1. RUNNING EXAMPLE: A SMALL TRAIN CONTROL SYSTEM 6 1.2. OVERVIEW OF THE VA APPROACH 7 1.3. RELATED WORK ON PATTERN-BASED AND COMPOSITIONAL VERIFIC- ATION 10 1.4. STRUCTURE OF THIS THESIS 13 1.5. ACKNOWLEDGEMENTS 15 2. PRELIMINARIES 17 2.1. CSP, OZ, AND DC 18 2.1.1. COMMUNICATING SEQUENTIAL PROCESSES 18 2.1.2. OBJECT-Z 22 2.1.3. DURATION CALCULUS 27 2.2. COMBINING CSP, OZ, AND DC INTO A PARAMETRIC LANGUAGE . 34 2.2.1. SYNTAX OF CSP-OZ-DC 34 2.2.2. SEMANTICS OF CSP-OZ-DC 37 2.2.3. RELATED COMBINED APPROACHES 40 2.3. PHASE EVENT AUTOMATA 41 2.3.1. SYNTAX AND SEMANTICS OF PHASE EVENT AUTOMATA . . 41 2.3.2. OPERATIONAL CSP-OZ-DC SEMANTICS IN TERMS OF PEA 47 3. EXTENDED CSP FOR VERIFICATION ARCHITECTURES 51 3.1. CSP PROCESSES FOR VERIFICATION ARCHITECTURES 52 3.1.1. CSP PROCESSES WITH DATA CONSTRAINTS 53 3.1.2. UNKNOWN PROCESSES 58 3.1.3. ASSUMPTIONS ON UNKNOWN PROCESSES 61 3.1.4. RUNNING EXAMPLE: A TRAIN CONTROL PROTOCOL . . . 62 3.2. PROPERTIES OF EXTENDED CSP 64 3.2.1. CONTINUOUS CSP OPERATORS 65 3.2.2. DISCONTINUITY OF PARALLEL COMPOSITION 67 3.3. NORMAL FORMS 69 3.4. DISCUSSION 74 IX BIBLIOGRAFISCHE INFORMATIONEN HTTP://D-NB.INFO/1016987560 DIGITALISIERT DURCH IMAGE 2 CONTENTS 3.4.1. PARAMETRIC SYSTEMS 74 3.4.2. SEMANTICS 75 3.4.3. RELATED WORK 76 4. A SEQUENT CALCULUS FOR VERIFICATION ARCHITECTURES 79 4.1. DYNAMIC LOGIC OVER CSP PROCESSES WITH DATA 80 4.2. SEQUENT CALCULUS 82 4.3. PROOF RULES 85 4.3.1. STRUCTURAL RULES 85 4.3.2. PROPOSITIONAL RULES 85 4.3.3. FIRST-ORDER RULES 86 4.3.4. SYMBOLIC EXECUTION OF DCSP FORMULAE 87 4.3.5. SYMBOLIC EXECUTION OF DCSP SPECIFICATIONS WITH UN- KNOWN PROCESSES 91 4.3.6. INDUCTION RULES 93 4.3.7. AUXILIARY DCSP RULES 96 4.4. SOUNDNESS OF THE CALCULUS 97 4.5. EMBEDDING OF A REAL-TIME LOGIC 113 4.5.1. CHECKING THE SIDE-CONDITIONS FOR THE BOX OPERATOR 113 4.5.2. CHECKING THE SIDE-CONDITIONS FOR THE DIAMOND OP- ERATOR 116 4.6. DISCUSSION 120 4.6.1. DISCUSSION OF THE VA APPROACH 120 4.6.2. RELATED WORK 121 5. REFINEMENT OF VERIFICATION ARCHITECTURES 127 5.1. REFINEMENT OF VERIFICATION ARCHITECTURES 127 5.2. SIMULATION OF PROCESSES 131 5.3. PROOF RULES FOR CHECKING REFINEMENT 133 5.4. SYNTACTICAL PROOF RULE FOR PROCESS REFINEMENT 138 5.5. PROPERTY INHERITANCE 144 5.6. DISCUSSION 147 6. LIMITATIONS AND EXTENSIONS 153 6.1. PARALLEL UNKNOWN PROCESSES 154 6.1.1. AUTOMATA-BASED SEMANTICS 155 6.1.2. TRANSLATION-BASED APPROACHES 159 6.1.3. RELY-GUARANTEE REASONING FOR PARALLEL UNKNOWNS . . 169 6.1.4. INSTANTIATING PARALLEL UNKNOWNS 176 IMAGE 3 CONTENTS 6.1.5. AN INTERPRETATION-BASED SEMANTICS FOR PARALLEL UN- KNOWNS 179 6.2. VERIFYING TIMING PROPERTIES 190 6.2.1. TEST PROCESSES FOR TIMING PROPERTIES 191 6.2.2. EXTENDED CALCULUS FOR TIMING PROPERTIES 193 6.3. EXAMINING COMPLETENESS 196 6.3.1. COMPLETENESS OF VA LANGUAGE 197 6.3.2. COMPLETENESS OF LOCAL ASSUMPTIONS 200 6.4. COMPLEMENTARY DECOMPOSITION TECHNIQUES 204 6.4.1. SLICING FORMAL SPECIFICATIONS 204 6.4.2. LAYERED COMPOSITION FOR TIMED PROTOCOLS 206 7. IMPLEMENTATION AND TOOLS 209 7.1. SYSPECT 210 7.1.1. UML PROFILE FOR REAL-TIME SYSTEMS 210 7.1.2. TOOL STRUCTURE 215 7.1.3. SYSPECT PLUG-INS 216 7.2. VERIFICATION WITH SYSPECT 217 7.2.1. TRANSITION CONSTRAINT SYSTEMS 217 7.2.2. VERIFICATION OF SYSPECT SPECIFICATIONS 220 7.2.3. SLICING CSP-OZ-DC SPECIFICATIONS IN SYSPECT . . . 223 7.2.4. FURTHER VERIFICATION PLUG-INS 223 7.3. SYSPECT VERIFICATION ARCHITECTURE PLUG-IN 223 7.3.1. MODELLING OF VAS 224 7.3.2. CSP-OZ-DC REPRESENTATION OF A VA 225 7.3.3. VERIFICATION OF VAS 225 7.4. DISCUSSION 228 8. CASE STUDIES 231 8.1. RUNNING EXAMPLE: SMALL TRAIN CONTROL SYSTEM 232 8.1.1. VERIFICATION OF THE ARCHITECTURE 233 8.1.2. INSTANTIATION BY A CSP-OZ-DC MODEL 234 8.2. EUROPEAN TRAIN CONTROL SYSTEM 238 8.2.1. CASE STUDY SCENARIO: EMERGENCIES IN TRAIN CONTROL SYSTEMS 238 8.2.2. PREVIOUS ETCS CASE STUDIES 239 8.2.3. VA FOR THE ETCS CASE STUDY 244 8.2.4. VA VERIFICATION 250 8.2.5. INSTANTIATING THE VA 258 XI IMAGE 4 CONTENTS 8.2.6. CHECKING THE INSTANTIATION WITH SYSPECT 263 8.2.7. DISCUSSION 268 9. CONCLUSIONS 271 9.1. DISCUSSION 272 9.2. ALTERNATIVE APPROACHES 276 9.3. PERSPECTIVES 278 A. CASE STUDY MATERIAL 283 A.I. TRAIN CONTROL SYSTEM OF THE RUNNING EXAMPLE 283 A.1.1. PROOF TREE FOR THE VA 283 A.1.2. CSP-OZ-DC MODEL OF THE TRAIN CONTROL SYSTEM . . 291 A.1.3. CSP-OZ-DC REPRESENTATION OF THE VA 295 A.1.4. ALTERNATIVE ARCHITECTURE WITHOUT ECSP 296 A.2. ETCS EMERGENCY MESSAGE CASE STUDY 299 A.2.1. ORIGINAL CSP-OZ-DC SPECIFICATION FROM [MFHR08] 299 A.2.2. VA PROOF TREE FOR THE ETCS CASE STUDY 303 A.2.3. MODIFIED CSP-OZ-DC SPECIFICATION MATCHING VA . . 311 BIBLIOGRAPHY 317 SEQUENT RULES 337 GLOSSARY OF SYMBOLS 339 INDEX 345 XLL
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series	Berichte aus dem Department für Informatik der Fakultät II - Informatik, Wirtschafts- und Rechtswissenschaften
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spellingShingle	Faber, Johannes Verification architectures for complex real time systems Berichte aus dem Department für Informatik der Fakultät II - Informatik, Wirtschafts- und Rechtswissenschaften Echtzeitverarbeitung (DE-588)4151002-1 gnd CSP (DE-588)4329097-8 gnd
subject_GND	(DE-588)4151002-1 (DE-588)4329097-8 (DE-588)4113937-9
title	Verification architectures for complex real time systems
title_auth	Verification architectures for complex real time systems
title_exact_search	Verification architectures for complex real time systems
title_full	Verification architectures for complex real time systems Johannes Faber
title_fullStr	Verification architectures for complex real time systems Johannes Faber
title_full_unstemmed	Verification architectures for complex real time systems Johannes Faber
title_short	Verification architectures for complex real time systems
title_sort	verification architectures for complex real time systems
topic	Echtzeitverarbeitung (DE-588)4151002-1 gnd CSP (DE-588)4329097-8 gnd
topic_facet	Echtzeitverarbeitung CSP Hochschulschrift
url	http://www.informatik.uni-oldenburg.de/download/Promotionen/Faber2011.pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=024505413&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
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work_keys_str_mv	AT faberjohannes verificationarchitecturesforcomplexrealtimesystems

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