Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
[San Rafael, Calif.]
Morgan & Claypool
2011
|
| Series: | Synthesis lectures on computer architecture
16 |
| Subjects: | |
| Links: | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022634292&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| Physical Description: | XIII, 195 S. graph. Darst. |
| ISBN: | 9781608455645 |
Staff View
MARC
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| 100 | 1 | |a Sorin, Daniel J. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a A primer on memory consistency and cache coherence |c Daniel J. Sorin, Mark D. Hill and David A. Wood |
| 264 | 1 | |a [San Rafael, Calif.] |b Morgan & Claypool |c 2011 | |
| 300 | |a XIII, 195 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
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| 490 | 1 | |a Synthesis lectures on computer architecture |v 16 | |
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| 700 | 1 | |a Hill, Mark D. |e Verfasser |4 aut | |
| 700 | 1 | |a Wood, David A. |e Verfasser |4 aut | |
| 776 | 0 | 8 | |i Erscheint auch als |n Online-Ausgabe |z 978-1-608-45565-2 |
| 830 | 0 | |a Synthesis lectures on computer architecture |v 16 |w (DE-604)BV023068349 |9 16 | |
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Record in the Search Index
| DE-BY-TUM_call_number | 0102 DAT 406f 2014 A 1153 |
|---|---|
| DE-BY-TUM_katkey | 1981324 |
| DE-BY-TUM_location | 01 |
| DE-BY-TUM_media_number | 040080396285 |
| _version_ | 1824442150249562112 |
| adam_text | Preface
.......................................................................................................................ix
1.
Introduction
to Consistency and Coherence
.........................................................1
1.1
Consistency (a.k.a., Memory Consistency, Memory Consistency Model,
or Memory Model)
..............................................................................................2
1.2
Coherence (a.k.a., Cache Coherence)
..................................................................4
1.3
A Consistency and Coherence Quiz
....................................................................6
1.4
What this Primer Does Not Do
..........................................................................6
2.
Coherence Basics
................................................................................................9
2.1
Baseline System Model
.......................................................................................9
2.2
The Problem: How Incoherence Could Possibly Occur
....................................10
2.3
Defining Coherence
..........................................................................................11
2.3.1
Maintaining the Coherence Invariants
..................................................13
2.3.2
The Granularity of Coherence
..............................................................13
2.3.3
The Scope of Coherence
.......................................................................15
2.4
References
..........................................................................................................15
3.
Memory Consistency Motivation and Sequential Consistency
............................17
3.1
Problems with Shared Memory Behavior
..........................................................17
3.2
What Is a Memory Consistency Model?
...........................................................20
3.3
Consistency vs. Coherence
................................................................................21
3.4
Basic Idea of Sequential Consistency (SC)
........................................................22
3.5
A Little SC Formalism
......................................................................................24
3.6
Naive SC Implementations
...............................................................................26
3.7
A Basic SC Implementation with Cache Coherence
.........................................27
3.8
Optimized SC Implementations with Cache Coherence
..................................29
3.9
Atomic Operations with SC
..............................................................................32
3.10
Putting it All Together: MIPS R10000
.............................................................33
A PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE
3.11
Further Reading Regarding SC
.........................................................................34
3.12
References
..........................................................................................................35
4.
Total Store Order and the x86 Memory Model
....................................................37
4.1
Motivation
ѓогТЅО/хбб
...................................................................................37
4.2
Basic Idea of TSO/X86
......................................................................................38
4.3
A Little TSO Formalism and an x86 Conjecture
..............................................42
4.4
Implementing
ТЅО/хбб
....................................................................................45
4.5
Atomic Instructions and Fences with TSO
.......................................................46
4.5.1
Atomic Instructions
...............................................................................46
4.5.2
Fences
....................................................................................................47
4.6
Further Reading RegardingTSO
......................................................................47
4.7
Comparing SC and TSO
...................................................................................48
4.8
References
..........................................................................................................49
5.
Relaxed Memory Consistency
............................................................................51
5.1
Motivation
.........................................................................................................51
5.1.1
Opportunities to Reorder Memory Operations
.....................................52
5.1.2
Opportunities to Exploit Reordering
....................................................53
5.2
An Example Relaxed Consistency Model
(XC)................................................55
5.2.1
The Basic Idea of the
XC
Model
...........................................................55
5.2.2
Examples Using Fences under
XC.........................................................56
5.2.3
Formalizing
XC.....................................................................................57
5.2.4
Examples Showing
XC
Operating Correctly
.........................................59
5.3
Implementing
XC.............................................................................................61
5.3.1
Atomic Instructions with
XC................................................................62
5.3.2
Fences with
XC.....................................................................................64
5.3.3
A Caveat
................................................................................................64
5.4
Sequential Consistency for Data-Race-Free Programs
.....................................64
5.5
Some Relaxed Model Concepts
.........................................................................68
5.5.1
Release Consistency
...............................................................................68
5.5.2
Causality and Write Atomicity
..............................................................69
5.6
A Relaxed Memory Model Case Study: IBM Power
........................................70
5.7
Further Reading and Commercial Relaxed Memory Models
............................74
5.7.1
Academic Literature
..............................................................................74
5.7.2
Commercial Models
..............................................................................74
CONTENTS
5.8
Comparing
Memory Models.............................................................................75
5.8.1
How Do Relaxed Memory Models Relate to Each Other and
TSOandSC?
........................................................................................75
5.8.2
How Good Are Relaxed Models?
..........................................................76
5.9
High-Level Language Models
..........................................................................76
5.10
References
..........................................................................................................79
6.
Coherence Protocols
.........................................................................................83
6.1
The Big Picture
.................................................................................................83
6.2
Specifying Coherence Protocols
........................................................................85
6.3
Example of a Simple Coherence Protocol
.........................................................86
6.4
Overview of Coherence Protocol Design Space
................................................88
6.4.1
States
.....................................................................................................88
6.4.2
Transactions
...........................................................................................92
6.4.3
Major Protocol Design Options
............................................................95
6.5
References
..........................................................................................................97
7.
Snooping Coherence Protocols
..........................................................................99
7.1
Introduction to Snooping
..................................................................................99
7.2
Baseline Snooping Protocol
.............................................................................103
7.2.1
High-Level Protocol Specification
......................................................104
7.2.2
Simple Snooping System Model: Atomic Requests,
Atomic Transactions
............................................................................104
7.2.3
Baseline Snooping System Model: Non-Atomic Requests,
Atomic Transactions
............................................................................109
7.2.4
Running Example
................................................................................113
7.2.5
Protocol Simplifications
.......................................................................114
7.3
Adding the Exclusive State
..............................................................................115
7.3.1
Motivation
...........................................................................................115
7.3.2
Getting to the Exclusive State
.............................................................115
7.3.3
High-Level Specification of Protocol
..................................................116
7.3.4
Detailed Specification
..........................................................................118
7.3.5
Running Example
................................................................................119
7.4
Adding the Owned State
.................................................................................119
7.4.1
Motivation
...........................................................................................119
7.4.2
High-Level Protocol Specification
......................................................121
xii
A PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE
7.4.3
Detailed Protocol Specification
...........................................................121
7.4.4
Running Example
................................................................................122
7.5
Non-
Atomic Bus
.............................................................................................123
7.5.1
Motivation
...........................................................................................124
7.5.2
In-Order vs. Out-of-Order Responses
................................................124
7.5.3
Non-Atomic System Model
................................................................124
7.5.4
An MSI Protocol with a Split-Transaction Bus
..................................126
7.5.5
An Optimized, Non-Stalling MSI Protocol with a
Split-Transaction Bus
..........................................................................130
7.6
Optimizations to the Bus Interconnection Network
.......................................132
7.6.1
Separate Non-Bus Network for Data Responses
.................................132
7.6.2
Logical Bus for Coherence Requests
...................................................133
7.7
Case Studies
....................................................................................................133
7.7.1
Sun Starfire
ЕЮ000
............................................................................133
7.7.2
IBM Power5
........................................................................................135
7.8
Discussion and the Future of Snooping
...........................................................137
7.9
References
........................................................................................................138
8.
Directory Coherence Protocols
........................................................................139
8.1
Introduction to Directory Protocols
................................................................139
8.2
Baseline Directory System
...............................................................................141
8.2.1
Directory System Model
.....................................................................141
8.2.2
High-level Protocol Specification
........................................................142
8.2.3
Avoiding Deadlock
..............................................................................144
8.2.4
Detailed Protocol Specification
...........................................................146
8.2.5
Protocol Operation
..............................................................................147
8.2.6
Protocol Simplifications
.......................................................................149
8.3
Adding the Exclusive State
..............................................................................150
8.3.1
High-Level Protocol Specification
......................................................150
8.3.2
Detailed Protocol Specification
...........................................................152
8.4
Adding the Owned State
.................................................................................153
8.4.1
High-Level Protocol Specification
.....................................................153
8.4.2
Detailed Protocol Specification
.........................................................155
8.5
Representing Directory State
..........................................................................156
8.5.1
Coarse Directory
................................................................................157
8.5.2
Limited Pointer Directory
..................................................................157
CONTENTS xiii
8.6 Directory
Organization...................................................................................
158
8.6.1 Directory Cache
Backed by DRAM
...................................................159
8.6.2
Inclusive
Directory Caches..................................................................160
8.6.3 Null Directory Cache
(with no backing store)
.....................................163
8.7
Performance and Scalability Optimizations
.....................................................163
8.7.1
Distributed Directories
........................................................................163
8.7.2
Non-Stalling Directory Protocols
........................................................164
8.7.3
Interconnection Networks without Point-to-Point Ordering
..............166
8.7.4
Silent vs. Non-Silent Evictions of Blocks in State
S
...........................168
8.8
Case Studies
....................................................................................................169
8.8.1
SGI Origin
2000.................................................................................169
8.8.2
Coherent
HyperTransport...................................................................171
8.8.3 HyperTransport
Assist
.........................................................................172
8.8.4
Intel QPI
.............................................................................................173
8.9
Discussion and the Future of Directory Protocols
...........................................175
8.10
References
........................................................................................................175
9.
Advanced Topics in Coherence
........................................................................177
9.1
System Models
................................................................................................177
9.1.1
Instruction Caches
...............................................................................177
9.1.2
Translation Lookaside Buffers (TLBs)
................................................178
9.1.3
Virtual Caches
.....................................................................................179
9.1.4
Write-Through Caches
.......................................................................180
9.1.5
Coherent Direct Memory Access (DMA)
...........................................180
9.1.6
Multi-Level Caches and Hierarchical Coherence Protocols
...............181
9.2
Performance Optimizations
.............................................................................184
9.2.1
Migratory Sharing Optimization
........................................................184
9.2.2
False Sharing Optimizations
...............................................................185
9.3
Maintaining Liveness
......................................................................................186
9.3.1
Deadlock
.............................................................................................186
9.3.2
Livelock
...............................................................................................189
9.3.3
Starvation
............................................................................................192
9.4
Token Coherence
.............................................................................................193
9.5
The Future of Coherence
................................................................................193
9.6
References
........................................................................................................193
Author Biographies
..................................................................................................195
|
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| id | DE-604.BV037482750 |
| illustrated | Illustrated |
| indexdate | 2024-12-20T15:17:51Z |
| institution | BVB |
| isbn | 9781608455645 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-022634292 |
| oclc_num | 734083517 |
| open_access_boolean | |
| owner | DE-473 DE-BY-UBG DE-Aug4 DE-634 DE-91G DE-BY-TUM DE-29T |
| owner_facet | DE-473 DE-BY-UBG DE-Aug4 DE-634 DE-91G DE-BY-TUM DE-29T |
| physical | XIII, 195 S. graph. Darst. |
| publishDate | 2011 |
| publishDateSearch | 2011 |
| publishDateSort | 2011 |
| publisher | Morgan & Claypool |
| record_format | marc |
| series | Synthesis lectures on computer architecture |
| series2 | Synthesis lectures on computer architecture |
| spellingShingle | Sorin, Daniel J. Hill, Mark D. Wood, David A. A primer on memory consistency and cache coherence Synthesis lectures on computer architecture Pufferspeicher (DE-588)4176324-5 gnd Konsistenz Informatik (DE-588)4214306-8 gnd Speicher Informatik (DE-588)4077653-0 gnd |
| subject_GND | (DE-588)4176324-5 (DE-588)4214306-8 (DE-588)4077653-0 |
| title | A primer on memory consistency and cache coherence |
| title_auth | A primer on memory consistency and cache coherence |
| title_exact_search | A primer on memory consistency and cache coherence |
| title_full | A primer on memory consistency and cache coherence Daniel J. Sorin, Mark D. Hill and David A. Wood |
| title_fullStr | A primer on memory consistency and cache coherence Daniel J. Sorin, Mark D. Hill and David A. Wood |
| title_full_unstemmed | A primer on memory consistency and cache coherence Daniel J. Sorin, Mark D. Hill and David A. Wood |
| title_short | A primer on memory consistency and cache coherence |
| title_sort | a primer on memory consistency and cache coherence |
| topic | Pufferspeicher (DE-588)4176324-5 gnd Konsistenz Informatik (DE-588)4214306-8 gnd Speicher Informatik (DE-588)4077653-0 gnd |
| topic_facet | Pufferspeicher Konsistenz Informatik Speicher Informatik |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022634292&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV023068349 |
| work_keys_str_mv | AT sorindanielj aprimeronmemoryconsistencyandcachecoherence AT hillmarkd aprimeronmemoryconsistencyandcachecoherence AT wooddavida aprimeronmemoryconsistencyandcachecoherence |
Branch Library Mathematics & Informatics
| Call Number: | 0102 DAT 406f 2014 A 1153 |
|---|---|
| Copy 1 | Available for loan On Shelf |