Logic restructuring for timing optimization in VLSI design:
Gespeichert in:
| Beteilige Person: | |
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| Format: | Hochschulschrift/Dissertation Buch |
| Sprache: | Englisch |
| Veröffentlicht: |
2007
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| Schlagwörter: | |
| Links: | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016247173&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| Umfang: | 107 Bl. graph. Darst. |
Internformat
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Datensatz im Suchindex
| _version_ | 1819340920548491264 |
|---|---|
| adam_text | LOGIC RESTRUCTURING FOR TIMING OPTIMIZATION IN VLSI DESIGN DISSERTATION
ZUR ERLANGUNG DES DOKTORGRADES DER MATHEMATISCH-NATURWISSENSCHAFTLICHEN
FAKULTAT DER RHEINISCHEN FRIEDRICH-WILHELMS-UNIVERSITAT BONN VORGELEGT
VON JIIRGEN WERBER AUS BOCHUM IM JULI 2007 ULB DARMSTADT
ILLLLLLLLLLLLLLLLLLLLLLL 16760390 CONTENTS 1 INTRODUCTION 5 2 THE
MATHEMATICS OF CIRCUIT DELAY 9 2.1 BOOLEAN FUNCTIONS AND CIRCUITS 9 2.2
CIRCUIT DELAY 11 2.3 ALPHABETIC CODE TREES WITH UNEQUAL LETTER COSTS 18
2.4 A FURTHER USEFUL RECURRENCE RELATION 31 2.5 AN ALGORITHM FOR
RESTRUCTURING PATH CIRCUITS 37 2.6 AN ASYMPTOTICALLY OPTIMAL
CONSTRUCTION FOR / 43 2.7 PREFIX COMPUTATIONS AND BINARY ADDITION 47 2.8
FORMULA SIZE AND DELAY 57 3 IMPLEMENTATION OF A LOGIC OPTIMIZATION
PACKAGE 61 3.1 TIMING ANALYSIS AND OPTIMIZATION IN PHYSICAL DESIGN 61
3.2 PREPARING INPUT INSTANCES FOR THE DYNAMIC PROGRAM 70 3.3
IMPLEMENTATION OF THE DYNAMIC PROGRAM ,,! . . ^ 74 3.4 ITERATIVE
APPLICATION OF THE ALGORITHM . II& 83 3.5 COMPUTATIONAL RESULTS .- .*
86 NOTATION INDEX 97 REFERENCES 99 SUMMARY 105
|
| any_adam_object | 1 |
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| dewey-full | 621.395 |
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| dewey-ones | 621 - Applied physics |
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| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Thesis Book |
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| illustrated | Illustrated |
| indexdate | 2024-12-20T13:07:19Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016247173 |
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| spellingShingle | Werber, Jürgen 1973- Logic restructuring for timing optimization in VLSI design Taktzeit (DE-588)4212485-2 gnd Schaltungslogik (DE-588)4179390-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4212485-2 (DE-588)4179390-0 (DE-588)4117388-0 (DE-588)4113937-9 |
| title | Logic restructuring for timing optimization in VLSI design |
| title_auth | Logic restructuring for timing optimization in VLSI design |
| title_exact_search | Logic restructuring for timing optimization in VLSI design |
| title_full | Logic restructuring for timing optimization in VLSI design von Jürgen Werber |
| title_fullStr | Logic restructuring for timing optimization in VLSI design von Jürgen Werber |
| title_full_unstemmed | Logic restructuring for timing optimization in VLSI design von Jürgen Werber |
| title_short | Logic restructuring for timing optimization in VLSI design |
| title_sort | logic restructuring for timing optimization in vlsi design |
| topic | Taktzeit (DE-588)4212485-2 gnd Schaltungslogik (DE-588)4179390-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Taktzeit Schaltungslogik VLSI Hochschulschrift |
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